Electronics > Projects, Designs, and Technical Stuff
Modern equivalent of 74HC4046 PLL?
BrianHG:
Also, when testing, lock your scope onto the Hsync input and place a second probe on the counter[5] output. Make sure you get a 50/50 duty cycle on that clock output through and just after the sync pulse. If it appears deformed in any way other than the potential +/-1.5ns jitter, you have done something wrong or have the wrong values from the scope's video output.
Extending the view across the picture should reveal a clock relatively locked to the pixels.
Miti:
How do you assign fast registers? When I do that in assignment editor, the PIN number disappears from the pin planner.
BrianHG:
Here is how you do it.
Enter the Assignment Editor.
Go to the bottom of the list and click on <<new>> like in my illustration #1.
Enter the NET pin name like in my illustration #2.
Select the assignment feature like in my illustration #3.
Select 'ON' like in my illustration #4. (Read added note...)
Click anywhere else, as if it is accepted, the new assignment line text will turn black.
Next, 'Save' in the file menu to save the addition to your assignments.
My guess is you might have entered a pin number instead of the net name assigned to the pin.
Miti:
Got it, thank you!
Actually what I did was to change the existing pin from location to fast register. Now I understand that both must be there.
BrianHG:
This way, you can change you pin out, but wherever you place the pin, Quartus knows that the 'net' name's associated logic needs to have it's logic cell located to the one right at the chosen IO pin creating as close to no delay as possible.
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