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Modern equivalent of 74HC4046 PLL?

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Miti:
If I set input frequency to 5.25MHz, I get a bandwidth error. I will make the up counter 5 bits and feed the second PLL from cnt[4], 10.5MHz.

BrianHG:
No problem.

Key 1 is when you scope the sync (ie trigger on sync in) into the FPGA and the counter's 5th bit out [bit 4 if you start at bit 0], you see a 50/50 duty cycle 10.5MHz square wave through the sync alignment time with only a +/- 1.5ns of jitter.  It shouldn't get any fatter of thinner on a high or low.  (Accounting for that total possible 3ns correction phase.  Remember, PLL#1 at 336 MHz isn't really locked to anything.)

Key 2, when scoping the output of the second PLL locked onto that 10.5MHz reference, it's slight jitter isn't really any worse.  The rest of your video design may now be run off of that PLLs outputs.  This output should not have that 3ns correction, but it will still have slight phase jitter noise as it slowly catches up with the introduced 3ns correction around 20 to 50 clock cycles later.  In any case, it should roast what you have shown so far with the dedicated external PLLs.

Miti:
I think I've got it. In "Without HSync", HSync is connected only to the scope, not to the FPGA.
I used my FY6600 and I know it is jittery on square by design.
Tomorrow I will try with the spectrum analyzer but I have to level shift from 5V to 3.3V.
I've also attached the raw code, please criticize mercilessly...  :-DD

Edit: I added 21MHz and 55.125MHz screen shots with frequency counter.



--- Code: ---module Default
(
//////////////////// Clock Input ////////////////////
CLOCK_24, // 24 MHz
EXT_CLOCK, // External Clock
RESET,
DRAM_CS_N, // SDRAM Chip Select
//////////////////// VIDEO IN ////////////////////////////
HSYNC_IN, // HSync in
OUT_10,
IN_10,
CLK_OUT_21,
CLK_OUT_55

);

//////////////////////// Clock Input ////////////////////////
input CLOCK_24; // 24 MHz
input EXT_CLOCK; // External Clock
input RESET;
//////////////////////// Push Button ////////////////////////

output DRAM_CS_N; // SDRAM Chip Select

////////////////////////////////////////////////////////////////////
input HSYNC_IN;
output OUT_10;
input IN_10;
output CLK_OUT_21;
output CLK_OUT_55;

wire CLK_336;

// All inout port turn to tri-state

assign DRAM_CS_N = 1'b1;

reg [4:0] CNT_PLL;

reg Pll_reg0;       
reg Pll_reg1;
 
wire Hsync_neg_pulse;

assign Hsync_neg_pulse = Pll_reg1 & (~Pll_reg0);
assign OUT_10 = CNT_PLL[4];

always@(posedge CLK_336)
begin
Pll_reg0 <= HSYNC_IN;
Pll_reg1 <= Pll_reg0;
end

always@(posedge CLK_336)
begin
if(Hsync_neg_pulse)
CNT_PLL <= 5'b00000;
else
CNT_PLL <= CNT_PLL + 1'b1;
end

Input_PLL u0 (
.inclk0(EXT_CLOCK),
//.inclk0(CLOCK_24),
.c0(CLK_336)
); // PLL module input clock

Output_PLL u1 (
.inclk0(IN_10),
.c0(CLK_OUT_21),
.c1(CLK_OUT_55)
); // PLL module output clock

endmodule

--- End code ---

BrianHG:
Raw code is fine, other than you do not need both 'always@(posedge CLK_336)', just 1 will do.

If it works fine on the scope, all you need to add is an adjustable 16 step shift on the reset (4 bits) and a 1 bit invert for the clock out (5th bit) which gives you a programmable 32 step/position phase offset for the 10.5Mhz clock so you may center you sample time on the center sweet-spot of the incoming video.

If you are sampling at 21MHz, then you only need the 4 bits for 16 positions.

Also, since you will probably be delaying the hsync input, pass an H-Sync out of your 336MHz after the programmable delay so that when you sample the hsync in the 21MHz section, you wont get horizontal sync jitter on a few lemon horizontal phase settings.

Tadaa, you now made the phase setting for the PLL in this IC:
https://www.ti.com/product/TVP7002

BrianHG:
Question:
If your scope is locking on the falling edge of the 'Sync in' only (yellow channel), why do I see 2 drop points 3ns apart?

I know the clocks might look messier if you sample only the 'Sync in' without that glitch, but it will tell you the degree of horizontal jitter noise a sample be during the width of a pixel.  That is if you zoom out to capture 2 h-syncs, then magnify into a few pixels so long as you scope has enough memory to not drop the sample rate.

Other than that, yes what I see roasts your old external PLLs.

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