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Modern equivalent of 74HC4046 PLL?

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Miti:

--- Quote from: BrianHG on July 22, 2020, 02:30:42 am ---Question:
If your scope is locking on the falling edge of the 'Sync in' only (yellow channel), why do I see 2 drop points 3ns apart?

I know the clocks might look messier if you sample only the 'Sync in' without that glitch, but it will tell you the degree of horizontal jitter noise a sample be during the width of a pixel.  That is if you zoom out to capture 2 h-syncs, then magnify into a few pixels so long as you scope has enough memory to not drop the sample rate.

Other than that, yes what I see roasts your old external PLLs.

--- End quote ---

That's exactly what I did. The screen shots are zoomed-in on the falling edge of the next HSync after the trigger point, ~64us delay.
The double falling edge of the HSync is coming from the FY6600 signal generator which is jittery on square wave on frequencies other than those with a period that is multiple of 4ns.
https://www.eevblog.com/forum/testgear/feeltech-fy6600-60mhz-2-ch-vco-function-arbitrary-waveform-signal-generator/1875/

That's why I said that I will try later with the HSync from the SA which is jitter free.

Miti:

--- Quote from: BrianHG on July 22, 2020, 02:30:42 am ---Other than that, yes what I see roasts your old external PLLs.

--- End quote ---

I totally agree! And about the title of this topic, I don't think you can find any more modern equivalent of HC4046 than this... :-DD

Miti:

--- Quote from: BrianHG on July 22, 2020, 02:23:02 am ---Raw code is fine, other than you do not need both 'always@(posedge CLK_336)', just 1 will do.

--- End quote ---

Like this?


--- Code: ---module Default
(
//////////////////// Clock Input ////////////////////
CLOCK_24, // 24 MHz
EXT_CLOCK, // External Clock
RESET,
DRAM_CS_N, // SDRAM Chip Select
//////////////////// VIDEO IN ////////////////////////////
HSYNC_IN, // HSync in
OUT_10,
IN_10,
CLK_OUT_21,
CLK_OUT_55

);

//////////////////////// Clock Input ////////////////////////
input CLOCK_24; // 24 MHz
input EXT_CLOCK; // External Clock
input RESET;
//////////////////////// Push Button ////////////////////////

output DRAM_CS_N; // SDRAM Chip Select

////////////////////////////////////////////////////////////////////
input HSYNC_IN;
output OUT_10;
input IN_10;
output CLK_OUT_21;
output CLK_OUT_55;

wire CLK_336;

// All inout port turn to tri-state

assign DRAM_CS_N = 1'b1;

reg [4:0] CNT_PLL;

reg Pll_reg0;       
reg Pll_reg1;
 
wire Hsync_neg_pulse;

assign Hsync_neg_pulse = Pll_reg1 & (~Pll_reg0);
assign OUT_10 = CNT_PLL[4];

always@(posedge CLK_336)
begin
Pll_reg0 <= HSYNC_IN;
Pll_reg1 <= Pll_reg0;

if(Hsync_neg_pulse)
CNT_PLL <= 5'b00000;
else
CNT_PLL <= CNT_PLL + 1'b1;
end

Input_PLL u0 (
.inclk0(EXT_CLOCK),
//.inclk0(CLOCK_24),
.c0(CLK_336)
); // PLL module input clock

Output_PLL u1 (
.inclk0(IN_10),
.c0(CLK_OUT_21),
.c1(CLK_OUT_55)
); // PLL module output clock

endmodule

--- End code ---

BrianHG:
Yes, that's perfectly fine.

BrianHG:

--- Quote from: Miti on July 22, 2020, 12:29:21 pm ---
--- Quote from: BrianHG on July 22, 2020, 02:30:42 am ---Other than that, yes what I see roasts your old external PLLs.

--- End quote ---

I totally agree! And about the title of this topic, I don't think you can find any more modern equivalent of HC4046 than this... :-DD

--- End quote ---
Well, if you really wanted to ultimately get it as good as possible, with some much better clever coding, like running 2 long period counters at the top 500MHz, one on the positive clock and the other on the negative clock, with an emulation of the PC2 on the 4046 either letting the counters run free, subtract 1 or add 1 once in a huge period of the HS coming in, we can shrink that +/- 1.5ns jitter down to 0.5ns.  However, if the old external PLL worked with that +/-10ns jitter, +/- 1.5 should be fine.  Just adding a second neg_clk counter to your current logic with a little careful DDR output trick feeding the Cyclone's second PLL would cut your current theoretical +/-1.5ns jitter in half.

Basically we would be making your design appear to be operating at 672MHz and we would be using second's PLLs low bandwidth to average 2 of the reference counters driving the same current output pin in a swapping MUX configuration, basically using the output pin the same way a DDR output is driven, except the swap from n-counter bit 5 to the p-counter bit 5 would only be done once after every 2 or 4 10.5mhz cycles.  To verify this would be functioning properly, you would want a scope with at least 5 GSPS.  (IE: if your scope maxes out at 500MSPS, how do you expect to debug the fine transition timing of a 672MHz clocked source?)


Either that, or on the output 10.5MHz output pin, feed it in series through a 1pf cap or even a FM radio 10,5MHz ceramic IF filter to a tuneable inductor/transistor amp with a bandwidth below 7KHz and feed that transistor's output into the CLK input back into the Cyclone erasing all remaining jitter so long as the transistor amp and circuit board analog noise is well isolated from the circuit.

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