Electronics > Projects, Designs, and Technical Stuff
Modern equivalent of 74HC4046 PLL?
Miti:
My DSO is Rigol DS1054Z, it is 1GS/s. Can’t I just observe the difference in jitter?
BrianHG:
Yes, you may be able to just make out a difference.
Remember, if your scope has the input bandwidth, with a 672MHz clocked output, your scope will only acquire 1 sample before the transition and part of one after. With a 5GSPS scope, you have 7 samples going through each clock output transition. The trick I mentioned involves monitoring the cyclone PLL bandwidth speed in the 'Low bandwidth' setting meaning we will want to measure jitter noise in the 0.2-0.5ns range. A perfect 1GSPS scope with 2 channels at 1GSPS (not an interleaved 500MSPS) could only measure 1ns of jitter per sweep. You actually do get even a bit more measurement resolution due to input analog bandwidth limitation and the scope's sinX/X interpolation.
First get your clock locked to your scope. If it's sync output is clean enough and your 24MHz feeding the Cyclone is clean enough, or the Cyclone PLLa power supply is free of noise, and you want to try the 672MHz PLL as an exercise to compare the jitter before and after, let's go right ahead. When I say clean enough, I mean you can see the distinct 3ns hops before the H-Sync re-alignment takes place on the second PLL's 21/10.5MHz output with the current 336MHz version.
I think at that point, you could not do any better unless you go back to a high quality vcxo and prepare a precision analog section for your PCB layout to eliminate all external EMI.
BrianHG:
Your 1054z is 500Msps with 2 channels on:
If you could still lock on sync in with channel #1, but turn channel 1 off and view the clock on channel #2 at 1GSa/s still locked to sync in on channel #1, then yes you can see much finer 2x detail.
This is one of those thing wheres when it comes to lower bandwidth/budget equipment, a 100Mhz analog scope might reveal more.
Remember your first single snapshot of the external PLLs, it looked clean until you locked onto the H-Sync and viewed the 2 signals at the synchronization point. the kind of jitter you are looking for is a slow long term analysis of a clock & how it's phase deviates over that 15KHz period. Not clock cycle to clock cycle which will look clean on any scope other than a spectrum analyzer with low frequency FM demodulated noise/purity measurement capabilities.
BrianHG:
--- Quote from: Miti on July 22, 2020, 12:29:21 pm ---
--- Quote from: BrianHG on July 22, 2020, 02:30:42 am ---Other than that, yes what I see roasts your old external PLLs.
--- End quote ---
I totally agree! And about the title of this topic, I don't think you can find any more modern equivalent of HC4046 than this... :-DD
--- End quote ---
Your topic and location was in the wrong place. I only found it by luck in with your other thread in the FPGA section.
If you made your topic in the FPGA section:
'Is it possible or Can you make a Cyclone PLL lock onto a 15KHz video source for a sampler clock?'
You would have never had to bother playing with any PLL ICs in the first place.
Though, you would never know how tricky it is to make those ICs operate in a clean behaved manner.
Miti:
--- Quote from: BrianHG on July 22, 2020, 07:38:25 pm ---Your 1054z is 500Msps with 2 channels on:
--- End quote ---
Yes but I can still see the jitter if I trigger on the output of interest and then move the trigger point to the left. Using only one channel.
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