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Modern equivalent of 74HC4046 PLL?

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BrianHG:
Judge the difference for yourself...

BrianHG:
This should roast your reference function generator's 4ns jitter.

Miti:

--- Quote from: BrianHG on July 23, 2020, 12:48:48 am ---Judge the difference for yourself...
(Attachment Link)

--- End quote ---

So half a clock shift vs one clock shift. I don't speak system verilog but seems easy to translate to verilog.
By DDR_DQ IO pin, you mean one of those pins marked with Q in the pin planner, but use it as 3.3V TTL default, right?

BrianHG:
To translate to verilog, except for the inputs, the 'logic' changes to 'reg'
input 'logic' changes to input wire.
'always_ff' changes to 'always'.

You can completely get rid of the 'clk_fix'.

Any IO voltage you use will work with 'ALT_DDIO_IN/OUT'.

As for the ALTDDIO_IN&OUT, they are in the mega IP store in the IO section.  Just set those up the same way you did your current PLLs in your existing code.  As long as you don't cross up the _h and _l, the code should make a clean clock.

Yes, on the top or bottom set of IOs for the FPGA, any IO pin would do.  Stick to 1 IO bank with a PLL in it for best results.  Just remember that in the future, you may want to reserve a dedicated PLL output pin if you will be clocking something like a ram chip.

Also, when feeding the 10.5MHz out back into the FPGA, the closest dedicated CLK input is usually the best choice.

The columns on the sides will also work, however, their response is a little slower.

I tried to simulate this design on Quartus Prime 18, LOL, it wouldn't even provide a clock output (it worked in functional mode, but not timing mode) and everything was dead due to Quartus believing that the PLL cant output a 336MHz clock though Quartus 9 seems to disagree.  An yet, your HDL was already clocking at 336MHz.

BrianHG:
To compare the DDR to the SDR version, just change this line:


--- Code: ---clk_out_h    <= sync_inl_reg ? counter_dl[4] : counter[4];
--- End code ---

to:


--- Code: ---clk_out_h    <=  counter[4];
--- End code ---

Or, make an new input wire ' enable_ddr ' and do this:


--- Code: ---clk_out_h    <= (sync_inl_reg && enable_ddr) ? counter_dl[4] : counter[4];
--- End code ---

So you may switch the DDR on and off in real-time when testing.

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