Electronics > Projects, Designs, and Technical Stuff
Modern equivalent of 74HC4046 PLL?
Miti:
--- Quote from: BrianHG on July 23, 2020, 12:08:04 am ---Now, because you are operating with a DDR input sampling at 672MHz when the theoretical limit is 500MHz, there were some things I had to set in Quartus to get reliable results.
--- End quote ---
So we’re exceeding the maximum frequency of Cyclone 4? Is that a good idea and can I expect repeatable results between chips and between boards?
BrianHG:
Well, we are keeping that 336MHz internal. It's only driving 18 registers. Quartus compile timing report says that the FMAX is well above the 400MHz space, but the 'Restricted FMAX' is 250MHz. This restriction is in place because they do not want you to drive IO pins with a signal greater than 250MHz. The problem here is if you try to output the 336MHz, even on a dedicated PLL output pin. That pin will need to open and close an N-channel and P-channel mosfet 672 million times a second without overlap, otherwise, that small transition time when both mosfets draws more current than what that section of the IC may be designed to do, including trying to charge and discharge the capacitance on the IO pin itself, and this current can get huge especially if you have a BGA with 128 IOs doing all this switching at the same time at the same speed. In fact, reading deep into the Intel Cyclone data sheets, there actually are total IO usage limits with particular current settings, or particular IO standard settings on the chip at top frequencies.
Tell me, does your current PLL design make the FPGA burn your finger?
For this PLL, we are getting away with it since our 1 output pin never exceeds switching at 10.5MHz and 1 input at 15KHz. If you need to output a clock of the first 336MHz PLL, though the 336 might will make it through, I would recommend making the PLL have a second output at 1/2, 168MHz, and feed that to the PLL output pin.
Here, I strategically chosen the IOs on 1 bank where a PLL is located running the MITI_PLL for a Cyclone III 144pin QFP, 3.3v LV TTL mode. (Basically equivalent to the Cyclone IV, but Quartus 9 only simulates Cyclone III and later versions of Quartus no longer simulate designs).
Now here is the new timing simulation with the strategic IO settings:
Notice how much better the DDR IO trick creates an in between clock cycle compared to my last simulation where the IO went anywhere on the FPGA.
When you make your design, I'm expecting you will not output a 336MHz clock.
If you are really afraid, you can always run the PLL at 168MHz instead and use the DDR trick to achieve an equivalent 336MHz function which you already have now without the DDR.
(I have a sneaky suspicion when you use the ALT_DDIO_xxx function, they are clocking the final pin IO register with either 2 phases from the PLL clock, or at 2X speed with a dedicated shift register to move that half phase data back onto your main CLK for your logic. I cannot achieve such clean DDR timing by any other means other than using the ALT_DDIO megafunction other than overclocking the design to 2x speed.)
BrianHG:
Intel/Altera may have just made it policy to kill the simulation results just at the clock reaches 250MHz since they figure no one would bother create such a simple 20 register design which can run above 250MHz , yet not do anything complicated. I guess it's a lack of imagination.
Miti:
--- Quote from: BrianHG on July 23, 2020, 04:49:53 pm ---Tell me, does your current PLL design make the FPGA burn your finger?
--- End quote ---
Far from that, the board only takes 80mA from 5V running only the PLL.
BrianHG:
Ok, so I guess we are waiting for you to place a resistor divider terminator for the scope 5v sync output into the cyclone & scope the PLL out in both SDR336MHz and the new DDR336MHz mode.
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