Electronics > Projects, Designs, and Technical Stuff

Modern equivalent of 74HC4046 PLL?

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BrianHG:
The Quartus Prime simulation failure is clearly a bug.  Here it is, right from the Cyclone IV data book:



Do not worry, we are completely in the clear unless your CycloneIV is the slowest low power version -9L...
Also notice my previous post FMAX and the -8 PLL maximum clock frequency.
Including the Fout to the dedicated PLL output pin which has a 472.5MHz limit.
I guess you can output the 336MHz if you want.

Miti:
Brian, something happened to the firsts attachment in #61, it is the same with the one in #65.

BrianHG:

--- Quote from: Miti on July 23, 2020, 09:03:57 pm ---Brian, something happened to the firsts attachment in #61, it is the same with the one in #65.

--- End quote ---
I know EEVblog has recently been corrupting attachments along may different posts for different people for some reason.
Give me a sec, I kept the originals just in case.  I'll re-upload the attachments right now.

Done, I checked them, they are OK as of 5:27 est GMT -5:00.

Miti:
And here it is. PLL1 is the one without DDIO, PLL2 is with DDIO. The screen shots are with HSync from the spectrum analyzer and 10 seconds persistence. They are captured at the trigger point and one line (next HSync pulse) after the trigger point. Apparently there is a bit of jitter in the SA clock as well but the results are much better. 5V supply current is 82mA.

Thanks Brian, this works great!!!

Edit: The forum does what it wants with the attachments. Arrgh!
Edit1: I added some pixel shots. There's always a 21MHz falling edge of the 21MHz clock right in the middle of the pixel. With a simple inverter I could make that the write clock for the dual port RAM. And that is an extra indication that the clock is locked on the pixel (well HSync) clock.

BrianHG:
10 second persistence, I don't think you will have trouble either sampling the video from the scope with that clock as you were zoomed into 5ns per division & I think your pixel width was 100ns.  Using the PLL2, the jitter seemed to be under 1 division, 2.5ns, a little worse than my predicted 1.4ns.  Though, with all the accumulated noise around, quality of scope's internal clock & TTL driver sync output, & I don't know if your FPGA PCB has a dedicated supply layer for the analog PLL supply, you are doing an order of magnitude better than the dedicated PLL with it's 25ns jitter.

Should have done the measurements with only 2 channels active so you get 500MS/s instead of the 250MS/s.

Ok, you have 1 chore left, just add the ability to shift the 21MHz output phase with a 4 bit input to you verilog code giving you 16 select-able positions + a pass through of the H_Sync_in with that carried delay to prevent horizontal alignment capture jitter.

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