Electronics > Projects, Designs, and Technical Stuff
Modern equivalent of 74HC4046 PLL?
BrianHG:
Also, you are zoomed in too close. What I really want to see is the beginning of the sync trigger at the left of the scope, and 20ns/div, only viewing the sync in and the DDIO output pin, not PLL#2. This will show us how the counter is behaving during hsync reset, like is it being squished or stretched. remember, that output DDIO output 10.5mhz reset takes effect something like 10-15ns after the h-sync in and we want to see a full cycle. You should be scoping only on every h-sync to view this one right.
This will prove that the clock of 21MHz divides into a perfect integer of the scopes H-sync.
Right now, you cannot see the reset trigger point as it takes place further to the right of you scope shot.
BrianHG:
--- Quote from: Miti on July 24, 2020, 02:29:33 am ---Edit1: I added some pixel shots. There's always a 21MHz falling edge of the 21MHz clock right in the middle of the pixel. With a simple inverter I could make that the write clock for the dual port RAM. And that is an extra indication that the clock is locked on the pixel (well HSync) clock.
--- End quote ---
Look carefully at your pixel clock scope shots. It's the rising edge of the cyan colored clock which always grabs the middle sweet spot of a pixel where it's analog vertical height stabilizes. I'm counting each video element on the screen being 2 pixels wide at 21MHz. The falling edge of the cyan clock is on the edges of a pixel. Yet, you wont find out much until you grad the data coming into the cyclone as the inputs have a delayed setup time. At 15Khz, this means your video coming out has a vertical resolution of something like 1024 pixels, ie 1024x240. A little odd. I would have suspected that the true sampling clock was 10.5 MHz making a screen res of 512x240.
Just like TTL logic using a resistor divider to drive a pseudo analog dac, it also seems that the video out of you scope falls slightly faster than it rises. Easy to see when you have a clean sampling clock overlayed on your oscilloscope image.
Miti:
--- Quote from: BrianHG on July 24, 2020, 02:55:57 am ---Also, you are zoomed in too close. What I really want to see is the beginning of the sync trigger at the left of the scope, and 20ns/div, only viewing the sync in and the DDIO output pin, not PLL#2. This will show us how the counter is behaving during hsync reset, like is it being squished or stretched. remember, that output DDIO output 10.5mhz reset takes effect something like 10-15ns after the h-sync in and we want to see a full cycle. You should be scoping only on every h-sync to view this one right.
This will prove that the clock of 21MHz divides into a perfect integer of the scopes H-sync.
Right now, you cannot see the reset trigger point as it takes place further to the right of you scope shot.
--- End quote ---
Like this? I can't see neither squish nor stretch.
Miti:
--- Quote from: BrianHG on July 24, 2020, 03:19:11 am ---Look carefully at your pixel clock scope shots. It's the rising edge of the cyan colored clock which always grabs the middle sweet spot of a pixel where it's analog vertical height stabilizes. I'm counting each video element on the screen being 2 pixels wide at 21MHz. The falling edge of the cyan clock is on the edges of a pixel. Yet, you wont find out much until you grad the data coming into the cyclone as the inputs have a delayed setup time. At 15Khz, this means your video coming out has a vertical resolution of something like 1024 pixels, ie 1024x240. A little odd. I would have suspected that the true sampling clock was 10.5 MHz making a screen res of 512x240.
--- End quote ---
Nope, the pixel clock is 10.5MHz, the oscillator is 21MHz. Pixel width is about 95us but I wanted to generate 21MHz exactly so I can have few edges to chose from. I will however implement the phase shifter.
BrianHG:
--- Quote from: Miti on July 24, 2020, 03:39:17 am ---
--- Quote from: BrianHG on July 24, 2020, 03:19:11 am ---Look carefully at your pixel clock scope shots. It's the rising edge of the cyan colored clock which always grabs the middle sweet spot of a pixel where it's analog vertical height stabilizes. I'm counting each video element on the screen being 2 pixels wide at 21MHz. The falling edge of the cyan clock is on the edges of a pixel. Yet, you wont find out much until you grad the data coming into the cyclone as the inputs have a delayed setup time. At 15Khz, this means your video coming out has a vertical resolution of something like 1024 pixels, ie 1024x240. A little odd. I would have suspected that the true sampling clock was 10.5 MHz making a screen res of 512x240.
--- End quote ---
Nope, the pixel clock is 10.5MHz, the oscillator is 21MHz. Pixel width is about 95us but I wanted to generate 21MHz exactly so I can have few edges to chose from. I will however implement the phase shifter.
--- End quote ---
This is what the '4 bit sample phase (now 5 bit)' adjustment is for. It shifts the 10.5MHz sample clock to 1 of 32 horizontal positions. Something your 21MHz 2 positions in a 10.5MHz clock cannot do.
As for your latest scope shot, that looks dead perfect.
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