Electronics > Projects, Designs, and Technical Stuff
Modern equivalent of 74HC4046 PLL?
BrianHG:
--- Quote from: Miti on July 26, 2020, 03:05:49 am ---
I assume you say that because you don't see the middle pulse in channel 1. Look at the gap in the thick yellow trace. They are both same frequency.
If you read from output port while you write to the input port, the image may blink for a moment. Also, when the output image starts in the middle of the input image due to drift, if there's a dramatic change in the input image, I think it would show. That's the flicker I was talking about.
--- End quote ---
Is this because you cannot retain a perfect H-sync from input to output image?
A delay of your output image by 1 or 2 lines of video should prevent this problem.
When you say blink, what do you mean?
Does the image jump vertically by a line, or a scrolling line jump, or something like that?
Since I don't know how you designed your architecture, I cannot foresee any approach I would use which would cause a blink of any sort. A delay of 2-3 lines of video, IE a 1/5000 of a sec delay from picture in to picture out is nothing at all. A delay of even 1 full frame at 1/50th of a second would not be registered or perceived by anyone.
Miti:
I thought about that right after I posted. The frames should not drift at all if HSync is present, is just that they start in random position relative to each other. Let me give it more thought.
BrianHG:
--- Quote from: Miti on July 26, 2020, 03:27:36 am ---I thought about that right after I posted. The frames should not drift at all if HSync is present, is just that they start in random position relative to each other. Let me give it more thought.
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Though this is easily solved, it still makes no difference if your picture out is delayed by 2-3 lines of picture.
You would literally have written 2-3 full lines in your 4 line buffer before the first one comes out.
You can also use the hsync coming into the sampler to reset the horizontal position counter of the hsync coming out of your VGA pattern generator. Or, if you look at my sampler code, you can make an output which pulses at any cord_x number which you can use to reset the output horizontal position of your VGA generator to align it the way you like. Same with the cord_y counter in my example code. You can make the your output vsync begin on line 0, 1, 2 or 3 or any vertical position of the source video coming in.
Miti:
Since we deviated pretty much from the initial PLL subject, I suggest we continue the discussion here:
https://www.eevblog.com/forum/projects/hp-8594e-replacing-the-green-crt-with-lcd/msg3022500/#msg3022500
That project will be the end application of this experiment plus these ones:
https://www.eevblog.com/forum/fpga/converting-a-two-level-analog-signal-to-two-bits-digital-in-cyclone-iv-orand-v/
https://www.eevblog.com/forum/fpga/adc-in-altera-cyclone-fpga/ which I will finalize one day using your code with shift registers.
Miti:
--- Quote from: BrianHG on July 20, 2020, 07:55:37 pm ---In my designs, I usually fast input & fast output register all IOs in my designs at the minor possible cost of reaching an FMAX.
--- End quote ---
I assume digital IOs? I don't think it makes sense assigning fast IO registers to LVDS IOs.
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