Electronics > Projects, Designs, and Technical Stuff
Modern equivalent of 74HC4046 PLL?
BrianHG:
--- Quote from: Miti on July 29, 2020, 02:06:46 am ---
--- Quote from: BrianHG on July 20, 2020, 07:55:37 pm ---In my designs, I usually fast input & fast output register all IOs in my designs at the minor possible cost of reaching an FMAX.
--- End quote ---
I assume digital IOs? I don't think it makes sense assigning fast IO registers to LVDS IOs.
--- End quote ---
Just go ahead.
Don't worry about FMAX, it's not like you have filled the FPGA to 98% logic registers full and you are trying to achieve an FMAX of 200MHz for the entire chip.
The fast in&out just directs the fitter where to optimize the location of the register D-flipflop on the FPGA fabric. Locating the flipflop closest to the IO if that flipflop is the one generating an output, or reading an input just makes that associated IO pin have the tightest possible timing.
Using a flipflop on the right hand side of the fpga to drive an IO pin on the left hand side of the fpga might mean an internal better FMAX, but, that IO pin will probably have a huge delay before that data becomes valid. Now unless you are willing to learn about defining the setup&hold times and constrained paths for IO pins, the fast IO is a cheap trick to tell to compiler to prioritize the IO pin's performance.
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