Author Topic: Modern equivalent of 74HC4046 PLL?  (Read 4771 times)

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Online BrianHG

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Re: Modern equivalent of 74HC4046 PLL?
« Reply #25 on: July 20, 2020, 02:32:07 pm »
You have got to be kidding me....
Ok, you will need to use 2 PLLs to get the 336MHz.
PLL #1 to switch from 25/50MHz to 21MHz.
PLL #2 to go from 21MHz to 336MHz.
Otherwise, you will end up with an odd clock frequency value of 336.11111MHz if you use 1 PLL.
Or, if you have a different reference oscillator which can divide cleanly into 336MHz like 27MHz, or 8MHz/16/24/32MHz, 54MHz, 13.5MHz ect...

If you have 3 PLLs in your Cyclone, this project will work fine with any oscillator you already have.
This changes is the sample clock is actually something slightly different like 10.4MHz or 10.6MHz.
« Last Edit: July 20, 2020, 02:41:46 pm by BrianHG »
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Offline Miti

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Re: Modern equivalent of 74HC4046 PLL?
« Reply #26 on: July 20, 2020, 06:41:56 pm »
No oscillator needed for his design since he is using it to capture so low resolution 2 bit color B&W image while having an FPGA with 4 plls in it which can run circles around a single pixel width with something like 10x oversampling.

I’ll be using a Cyclone 4 in TQFP 144 package. It has two PLLs only.
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Offline Miti

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Re: Modern equivalent of 74HC4046 PLL?
« Reply #27 on: July 20, 2020, 06:52:11 pm »
You have got to be kidding me....
Ok, you will need to use 2 PLLs to get the 336MHz.
PLL #1 to switch from 25/50MHz to 21MHz.
PLL #2 to go from 21MHz to 336MHz.
Otherwise, you will end up with an odd clock frequency value of 336.11111MHz if you use 1 PLL.
Or, if you have a different reference oscillator which can divide cleanly into 336MHz like 27MHz, or 8MHz/16/24/32MHz, 54MHz, 13.5MHz ect...

If you have 3 PLLs in your Cyclone, this project will work fine with any oscillator you already have.
This changes is the sample clock is actually something slightly different like 10.4MHz or 10.6MHz.

Don’t worry, I’ve checked, 24MHz would do it.
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Online BrianHG

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Re: Modern equivalent of 74HC4046 PLL?
« Reply #28 on: July 20, 2020, 07:13:55 pm »
You have got to be kidding me....
Ok, you will need to use 2 PLLs to get the 336MHz.
PLL #1 to switch from 25/50MHz to 21MHz.
PLL #2 to go from 21MHz to 336MHz.
Otherwise, you will end up with an odd clock frequency value of 336.11111MHz if you use 1 PLL.
Or, if you have a different reference oscillator which can divide cleanly into 336MHz like 27MHz, or 8MHz/16/24/32MHz, 54MHz, 13.5MHz ect...

If you have 3 PLLs in your Cyclone, this project will work fine with any oscillator you already have.
This changes is the sample clock is actually something slightly different like 10.4MHz or 10.6MHz.

Don’t worry, I’ve checked, 24MHz would do it.
Yup, 24 MHz multiplies x 14 to perfectly make 336MHz.
2 PLLs will work fine.
Making a 6 bit counter run at 336MHz will also be not problem.
Since your 336MHz clock will either be ever so slightly slower or faster than the scope's H-sync generated from the 10.5MHz, your final total correction jitter will be an occasional 2.976ns skip in 1 direction.

     I haven't a clue, but if you can get a 6 bit counter running at 672MHz, this occasional corrective skip will be down at 1.488ns at a time.  Having a code configured fixed phase alignment setting wouldn't be a problem, but you most likely could not get a software controlled one operating at 672MHz unless it's a -6 Cyclone, or just something ingeniously designed.

     Clocking a second PLL from the top bit of the 6 bit counter with the low bandwidth loop filter will make that PLL slowly adjust it's rate to align to these skips filtering out any abrupt transition step.  That second PLL can simultaneously make you sample clock and video output clock.

     Though, if you have a little flexibility on that VGA clock, like running it at 52.5MHz and using a different horizontal sync, front, and back porch values, this figure squarely divides into selecting a single core clock of 105MHz.  Where you output the VGA every second clock and sample video every 5th or 10th clock.
« Last Edit: July 20, 2020, 07:28:12 pm by BrianHG »
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Online BrianHG

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Re: Modern equivalent of 74HC4046 PLL?
« Reply #29 on: July 20, 2020, 07:55:37 pm »
Oh, 1 thing... You will need to drive an output pin with the counter bit[5], then tie that pin to an input to drive the second PLL.  Quartus doesn't like an internal logic cell driving the clk input of a PLL.

Make sure you make assignments:
fast output register for the counter bit[5]
and
fast input register for the sync inputs and video data inputs.

This way, as long as you register the inputs to a PLL clock as well as registered output, each compile build you make will have identical phase timing.  Otherwise, after each build, depending where the fitter places the logic, your phase delay will drift due to internal routing of the FPGA fabric.

In my designs, I usually fast input & fast output register all IOs in my designs at the minor possible cost of reaching an FMAX.  The usual fix is just an additional pipe-lined clocked register.
« Last Edit: July 20, 2020, 09:42:35 pm by BrianHG »
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Online BrianHG

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Re: Modern equivalent of 74HC4046 PLL?
« Reply #30 on: July 20, 2020, 09:49:00 pm »
Also, when testing, lock your scope onto the Hsync input and place a second probe on the counter[5] output.  Make sure you get a 50/50 duty cycle on that clock output through and just after the sync pulse.  If it appears deformed in any way other than the potential +/-1.5ns jitter, you have done something wrong or have the wrong values from the scope's video output.

Extending the view across the picture should reveal a clock relatively locked to the pixels.
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Offline Miti

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Re: Modern equivalent of 74HC4046 PLL?
« Reply #31 on: July 21, 2020, 01:30:00 am »
How do you assign fast registers? When I do that in assignment editor, the PIN number disappears from the pin planner.
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Online BrianHG

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Re: Modern equivalent of 74HC4046 PLL?
« Reply #32 on: July 21, 2020, 01:49:12 am »
Here is how you do it.
Enter the Assignment Editor.

Go to the bottom of the list and click on <<new>> like in my illustration #1.
Enter the NET pin name like in my illustration #2.
Select the assignment feature like in my illustration #3.
Select 'ON' like in my illustration #4.  (Read added note...)

Click anywhere else, as if it is accepted, the new assignment line text will turn black.
Next, 'Save' in the file menu to save the addition to your assignments.

My guess is you might have entered a pin number instead of the net name assigned to the pin.
« Last Edit: July 21, 2020, 01:52:29 am by BrianHG »
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Offline Miti

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Re: Modern equivalent of 74HC4046 PLL?
« Reply #33 on: July 21, 2020, 01:52:48 am »
Got it, thank you!
Actually what I did was to change the existing pin from location to fast register. Now I understand that both must be there.
« Last Edit: July 21, 2020, 01:54:23 am by Miti »
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Online BrianHG

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Re: Modern equivalent of 74HC4046 PLL?
« Reply #34 on: July 21, 2020, 02:02:43 am »
This way, you can change you pin out, but wherever you place the pin, Quartus knows that the 'net' name's associated logic needs to have it's logic cell located to the one right at the chosen IO pin creating as close to no delay as possible.
 
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Offline Miti

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Re: Modern equivalent of 74HC4046 PLL?
« Reply #35 on: July 21, 2020, 07:20:08 pm »
If I set input frequency to 5.25MHz, I get a bandwidth error. I will make the up counter 5 bits and feed the second PLL from cnt[4], 10.5MHz.
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Online BrianHG

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Re: Modern equivalent of 74HC4046 PLL?
« Reply #36 on: July 21, 2020, 08:46:59 pm »
No problem.

Key 1 is when you scope the sync (ie trigger on sync in) into the FPGA and the counter's 5th bit out [bit 4 if you start at bit 0], you see a 50/50 duty cycle 10.5MHz square wave through the sync alignment time with only a +/- 1.5ns of jitter.  It shouldn't get any fatter of thinner on a high or low.  (Accounting for that total possible 3ns correction phase.  Remember, PLL#1 at 336 MHz isn't really locked to anything.)

Key 2, when scoping the output of the second PLL locked onto that 10.5MHz reference, it's slight jitter isn't really any worse.  The rest of your video design may now be run off of that PLLs outputs.  This output should not have that 3ns correction, but it will still have slight phase jitter noise as it slowly catches up with the introduced 3ns correction around 20 to 50 clock cycles later.  In any case, it should roast what you have shown so far with the dedicated external PLLs.
« Last Edit: July 21, 2020, 08:54:15 pm by BrianHG »
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Offline Miti

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Re: Modern equivalent of 74HC4046 PLL?
« Reply #37 on: July 22, 2020, 01:58:58 am »
I think I've got it. In "Without HSync", HSync is connected only to the scope, not to the FPGA.
I used my FY6600 and I know it is jittery on square by design.
Tomorrow I will try with the spectrum analyzer but I have to level shift from 5V to 3.3V.
I've also attached the raw code, please criticize mercilessly...  :-DD

Edit: I added 21MHz and 55.125MHz screen shots with frequency counter.


Code: [Select]
module Default
(
//////////////////// Clock Input ////////////////////
CLOCK_24, // 24 MHz
EXT_CLOCK, // External Clock
RESET,
DRAM_CS_N, // SDRAM Chip Select
//////////////////// VIDEO IN ////////////////////////////
HSYNC_IN, // HSync in
OUT_10,
IN_10,
CLK_OUT_21,
CLK_OUT_55

);

//////////////////////// Clock Input ////////////////////////
input CLOCK_24; // 24 MHz
input EXT_CLOCK; // External Clock
input RESET;
//////////////////////// Push Button ////////////////////////

output DRAM_CS_N; // SDRAM Chip Select

////////////////////////////////////////////////////////////////////
input HSYNC_IN;
output OUT_10;
input IN_10;
output CLK_OUT_21;
output CLK_OUT_55;

wire CLK_336;

// All inout port turn to tri-state

assign DRAM_CS_N = 1'b1;

reg [4:0] CNT_PLL;

reg Pll_reg0;       
reg Pll_reg1;
 
wire Hsync_neg_pulse;

assign Hsync_neg_pulse = Pll_reg1 & (~Pll_reg0);
assign OUT_10 = CNT_PLL[4];

always@(posedge CLK_336)
begin
Pll_reg0 <= HSYNC_IN;
Pll_reg1 <= Pll_reg0;
end

always@(posedge CLK_336)
begin
if(Hsync_neg_pulse)
CNT_PLL <= 5'b00000;
else
CNT_PLL <= CNT_PLL + 1'b1;
end

Input_PLL u0 (
.inclk0(EXT_CLOCK),
//.inclk0(CLOCK_24),
.c0(CLK_336)
); // PLL module input clock

Output_PLL u1 (
.inclk0(IN_10),
.c0(CLK_OUT_21),
.c1(CLK_OUT_55)
); // PLL module output clock

endmodule
« Last Edit: July 22, 2020, 02:06:44 am by Miti »
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Online BrianHG

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Re: Modern equivalent of 74HC4046 PLL?
« Reply #38 on: July 22, 2020, 02:23:02 am »
Raw code is fine, other than you do not need both 'always@(posedge CLK_336)', just 1 will do.

If it works fine on the scope, all you need to add is an adjustable 16 step shift on the reset (4 bits) and a 1 bit invert for the clock out (5th bit) which gives you a programmable 32 step/position phase offset for the 10.5Mhz clock so you may center you sample time on the center sweet-spot of the incoming video.

If you are sampling at 21MHz, then you only need the 4 bits for 16 positions.

Also, since you will probably be delaying the hsync input, pass an H-Sync out of your 336MHz after the programmable delay so that when you sample the hsync in the 21MHz section, you wont get horizontal sync jitter on a few lemon horizontal phase settings.

Tadaa, you now made the phase setting for the PLL in this IC:
https://www.ti.com/product/TVP7002

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Online BrianHG

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Re: Modern equivalent of 74HC4046 PLL?
« Reply #39 on: July 22, 2020, 02:30:42 am »
Question:
If your scope is locking on the falling edge of the 'Sync in' only (yellow channel), why do I see 2 drop points 3ns apart?

I know the clocks might look messier if you sample only the 'Sync in' without that glitch, but it will tell you the degree of horizontal jitter noise a sample be during the width of a pixel.  That is if you zoom out to capture 2 h-syncs, then magnify into a few pixels so long as you scope has enough memory to not drop the sample rate.

Other than that, yes what I see roasts your old external PLLs.
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Offline Miti

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Re: Modern equivalent of 74HC4046 PLL?
« Reply #40 on: July 22, 2020, 03:19:48 am »
Question:
If your scope is locking on the falling edge of the 'Sync in' only (yellow channel), why do I see 2 drop points 3ns apart?

I know the clocks might look messier if you sample only the 'Sync in' without that glitch, but it will tell you the degree of horizontal jitter noise a sample be during the width of a pixel.  That is if you zoom out to capture 2 h-syncs, then magnify into a few pixels so long as you scope has enough memory to not drop the sample rate.

Other than that, yes what I see roasts your old external PLLs.

That's exactly what I did. The screen shots are zoomed-in on the falling edge of the next HSync after the trigger point, ~64us delay.
The double falling edge of the HSync is coming from the FY6600 signal generator which is jittery on square wave on frequencies other than those with a period that is multiple of 4ns.
https://www.eevblog.com/forum/testgear/feeltech-fy6600-60mhz-2-ch-vco-function-arbitrary-waveform-signal-generator/1875/

That's why I said that I will try later with the HSync from the SA which is jitter free.
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Offline Miti

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Re: Modern equivalent of 74HC4046 PLL?
« Reply #41 on: July 22, 2020, 12:29:21 pm »
Other than that, yes what I see roasts your old external PLLs.

I totally agree! And about the title of this topic, I don't think you can find any more modern equivalent of HC4046 than this... :-DD
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Offline Miti

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Re: Modern equivalent of 74HC4046 PLL?
« Reply #42 on: July 22, 2020, 12:40:21 pm »
Raw code is fine, other than you do not need both 'always@(posedge CLK_336)', just 1 will do.

Like this?

Code: [Select]
module Default
(
//////////////////// Clock Input ////////////////////
CLOCK_24, // 24 MHz
EXT_CLOCK, // External Clock
RESET,
DRAM_CS_N, // SDRAM Chip Select
//////////////////// VIDEO IN ////////////////////////////
HSYNC_IN, // HSync in
OUT_10,
IN_10,
CLK_OUT_21,
CLK_OUT_55

);

//////////////////////// Clock Input ////////////////////////
input CLOCK_24; // 24 MHz
input EXT_CLOCK; // External Clock
input RESET;
//////////////////////// Push Button ////////////////////////

output DRAM_CS_N; // SDRAM Chip Select

////////////////////////////////////////////////////////////////////
input HSYNC_IN;
output OUT_10;
input IN_10;
output CLK_OUT_21;
output CLK_OUT_55;

wire CLK_336;

// All inout port turn to tri-state

assign DRAM_CS_N = 1'b1;

reg [4:0] CNT_PLL;

reg Pll_reg0;       
reg Pll_reg1;
 
wire Hsync_neg_pulse;

assign Hsync_neg_pulse = Pll_reg1 & (~Pll_reg0);
assign OUT_10 = CNT_PLL[4];

always@(posedge CLK_336)
begin
Pll_reg0 <= HSYNC_IN;
Pll_reg1 <= Pll_reg0;

if(Hsync_neg_pulse)
CNT_PLL <= 5'b00000;
else
CNT_PLL <= CNT_PLL + 1'b1;
end

Input_PLL u0 (
.inclk0(EXT_CLOCK),
//.inclk0(CLOCK_24),
.c0(CLK_336)
); // PLL module input clock

Output_PLL u1 (
.inclk0(IN_10),
.c0(CLK_OUT_21),
.c1(CLK_OUT_55)
); // PLL module output clock

endmodule
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Online BrianHG

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Re: Modern equivalent of 74HC4046 PLL?
« Reply #43 on: July 22, 2020, 01:08:35 pm »
Yes, that's perfectly fine.
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Online BrianHG

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Re: Modern equivalent of 74HC4046 PLL?
« Reply #44 on: July 22, 2020, 04:32:45 pm »
Other than that, yes what I see roasts your old external PLLs.

I totally agree! And about the title of this topic, I don't think you can find any more modern equivalent of HC4046 than this... :-DD
Well, if you really wanted to ultimately get it as good as possible, with some much better clever coding, like running 2 long period counters at the top 500MHz, one on the positive clock and the other on the negative clock, with an emulation of the PC2 on the 4046 either letting the counters run free, subtract 1 or add 1 once in a huge period of the HS coming in, we can shrink that +/- 1.5ns jitter down to 0.5ns.  However, if the old external PLL worked with that +/-10ns jitter, +/- 1.5 should be fine.  Just adding a second neg_clk counter to your current logic with a little careful DDR output trick feeding the Cyclone's second PLL would cut your current theoretical +/-1.5ns jitter in half.

Basically we would be making your design appear to be operating at 672MHz and we would be using second's PLLs low bandwidth to average 2 of the reference counters driving the same current output pin in a swapping MUX configuration, basically using the output pin the same way a DDR output is driven, except the swap from n-counter bit 5 to the p-counter bit 5 would only be done once after every 2 or 4 10.5mhz cycles.  To verify this would be functioning properly, you would want a scope with at least 5 GSPS.  (IE: if your scope maxes out at 500MSPS, how do you expect to debug the fine transition timing of a 672MHz clocked source?)


Either that, or on the output 10.5MHz output pin, feed it in series through a 1pf cap or even a FM radio 10,5MHz ceramic IF filter to a tuneable inductor/transistor amp with a bandwidth below 7KHz and feed that transistor's output into the CLK input back into the Cyclone erasing all remaining jitter so long as the transistor amp and circuit board analog noise is well isolated from the circuit.
« Last Edit: July 22, 2020, 06:21:49 pm by BrianHG »
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Offline Miti

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Re: Modern equivalent of 74HC4046 PLL?
« Reply #45 on: July 22, 2020, 06:33:15 pm »
My DSO is Rigol DS1054Z, it is 1GS/s. Can’t I just observe the difference in jitter?
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Online BrianHG

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Re: Modern equivalent of 74HC4046 PLL?
« Reply #46 on: July 22, 2020, 07:19:30 pm »
Yes, you may be able to just make out a difference.
Remember, if your scope has the input bandwidth, with a 672MHz clocked output, your scope will only acquire 1 sample before the transition and part of one after.  With a 5GSPS scope, you have 7 samples going through each clock output transition.  The trick I mentioned involves monitoring the cyclone PLL bandwidth speed in the 'Low bandwidth' setting meaning we will want to measure jitter noise in the 0.2-0.5ns range.  A perfect 1GSPS scope with 2 channels at 1GSPS (not an interleaved 500MSPS) could only measure 1ns of jitter per sweep.  You actually do get even a bit more measurement resolution due to input analog bandwidth limitation and the scope's sinX/X interpolation.

First get your clock locked to your scope.  If it's sync output is clean enough and your 24MHz feeding the Cyclone is clean enough, or the Cyclone PLLa power supply is free of noise, and you want to try the 672MHz PLL as an exercise to compare the jitter before and after, let's go right ahead.  When I say clean enough, I mean you can see the distinct 3ns hops before the H-Sync re-alignment takes place on the second PLL's 21/10.5MHz output with the current 336MHz version.

I think at that point, you could not do any better unless you go back to a high quality vcxo and prepare a precision analog section for your PCB layout to eliminate all external EMI.
« Last Edit: July 22, 2020, 08:04:59 pm by BrianHG »
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Online BrianHG

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Re: Modern equivalent of 74HC4046 PLL?
« Reply #47 on: July 22, 2020, 07:38:25 pm »
Your 1054z is 500Msps with 2 channels on:
[attachimg=1]

If you could still lock on sync in with channel #1, but turn channel 1 off and view the clock on channel #2 at 1GSa/s still locked to sync in on channel #1, then yes you can see much finer 2x detail.

This is one of those thing wheres when it comes to lower bandwidth/budget equipment, a 100Mhz analog scope might reveal more.

Remember your first single snapshot of the external PLLs, it looked clean until you locked onto the H-Sync and viewed the 2 signals at the synchronization point.  the kind of jitter you are looking for is a slow long term analysis of a clock & how it's phase deviates over that 15KHz period.  Not clock cycle to clock cycle which will look clean on any scope other than a spectrum analyzer with low frequency FM demodulated noise/purity measurement capabilities.

« Last Edit: July 22, 2020, 08:10:42 pm by BrianHG »
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Re: Modern equivalent of 74HC4046 PLL?
« Reply #48 on: July 22, 2020, 07:55:18 pm »
Other than that, yes what I see roasts your old external PLLs.

I totally agree! And about the title of this topic, I don't think you can find any more modern equivalent of HC4046 than this... :-DD
Your topic and location was in the wrong place.  I only found it by luck in with your other thread in the FPGA section.

If you made your topic in the FPGA section:
'Is it possible or Can you make a Cyclone PLL lock onto a 15KHz video source for a sampler clock?'
You would have never had to bother playing with any PLL ICs in the first place.

Though, you would never know how tricky it is to make those ICs operate in a clean behaved manner.
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Offline Miti

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Re: Modern equivalent of 74HC4046 PLL?
« Reply #49 on: July 22, 2020, 08:19:56 pm »
Your 1054z is 500Msps with 2 channels on:

Yes but I can still see the jitter if I trigger on the output of interest and then move the trigger point to the left. Using only one channel.
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