Z80 address line 'noise' [SOLVED]

[SirWhy]

So after years of tinkering with 8-bit micros and kits, I'm taking the plunge and making my own homebrew Z80 system. Found a Z84C0020PEC in my parts bin and decided to build the minimal test circuit found here.

All is mostly well, the address lines are acting like a big binary counter however when probing the lines I found something peculiar. A0 - A6 have signals as expected, however A7 on wards seems to be some amplitude modulated signal. Since I don't know the source I have dubbed it 'noise' however since it's a fairly clean squarewave I have my doubts, scope screenshots have been attatched (first is A6, a normal address line, second is A7, third is a close up of A7).

Anyone have any idea? Is it normal and do I have to worry about it? I know the Z80 has DRAM circuitry built in, so is this just part of it?

Thanks

[jimon]

My guess is that they might be open collector of some sort (or floating in any other way), try pulling them down/up with 1-10k resistor to ground/5v and see what happens.
Though I've checked the data sheet and it's supposed to be CMOS, so not really understand why they are floating, might be some special mode?

[jimon]

Nwm, just read the page about test jig:

During the last half of the Instruction Opcode Fetch a Refresh address is placed on the lower 7 bits of the Address bus. This can make the upper 9 bits appear as if they are oscillating in respect to the clock since they are driven low during that portion of the cycle. If you only take the state of the address bus when /M1 is active, you will see the appropriate memory address is on the bus.
This seems to be different from type of CPU to CPU, mine did what I have measured on A0 to A2 and so far...

[SirWhy]

A fresh set of eyes always seems to point out something I overlook. Moral of the story, don't skim pages you're copying the test rig from!
As this is documented it bodes well for my Z80 adventures to come. Thanks

[Bendba]

Hi,
I came here for the same problem, first try with a Z80 (One manufactured by Sharp) I made a test circuit seen it is a salvaged part. And A0 to A6 count properly but A7 to A15 flicker.
So I slowed the clock down to 3Hz and here is what I could see, if that's any useful information to anyone:
The upper address output blink in sync with REFSH (pin 28),
And I think (I can't confirm because it appears that I just fried my processor probing around and shorting REFSH to grounds,)  in opposition with M1 (pin 27) and out of phase with MREQ (pin 19)

I  actually can confirm, I just happened to move a probing wire around a pin at the moment the processor decided to bug because my 9v battery powering the board ran low.

And there is a bonus question. I accidently plugged a Z80 SIO chip in place of the processor in the test circuit.
The power pins are at different places on the two chips. How high are the chances I fried the SIO chip?

[Fungus]

All is mostly well, the address lines are acting like a big binary counter however when probing the lines I found something peculiar. A0 - A6 have signals as expected, however A7 on wards seems to be some amplitude modulated signal. Since I don't know the source I have dubbed it 'noise' however since it's a fairly clean squarewave I have my doubts, scope screenshots have been attatched (first is A6, a normal address line, second is A7, third is a close up of A7).

Anyone have any idea? Is it normal and do I have to worry about it? I know the Z80 has DRAM circuitry built in, so is this just part of it?

Yes, it's part of the DRAM refresh. The lower 8 address lines will 'count' on alternate clock cycles. The other pins are probably floating.

[Bendba]

I'm a bit intrigued there. I thought the z80 was a static processor, hence no internal dram. If it does have a dram, how does it keep its state at low clock frequency?
The second thing I can't quite figure is why that behavior is observed on A7 to A15 and not A8 to A15, A7 being part of the lower significant byte.

[bitslice]

I'm a bit intrigued there. I thought the z80 was a static processor, hence no internal dram. If it does have a dram, how does it keep its state at low clock frequency?
The second thing I can't quite figure is why that behavior is observed on A7 to A15 and not A8 to A15, A7 being part of the lower significant byte.

the refresh function is for external dram

the contents of the I register are placed on the upper 8 bits of the address bus, which might explain the flicker seen

Yes, it's part of the DRAM refresh. The lower 8 address lines will 'count' on alternate clock cycles. The other pins are probably floating.

actually only the lower 7 bits of the R register are output as a refresh cycle, and the R resister is incremented for every instruction.
I think for RAMs bigger than 16K the dram holds the counter itself.

[Bendba]

Thanks for the information, that's good to know and probably going to save some debugging time.
Using a latching buffer on the address bus would work too wouldn't it? (I'm not really planning on running higher than 5 mHz if I get a newer cmos version so propagation delay shouldn't be an issue)

[bitslice]

Using a latching buffer on the address bus would work too wouldn't it?

Not sure if you mean as part of a refresh circuit or as simply buffering the address lines?

[Bendba]

Sorry, that wasn't really clear. Yes, I'm talking about buffering the address lines.

I'm not really into dynamic ram yet, I still try to understand all the ins and outs of the refreshing. I wish I could find a small dram chip (something like 256 bytes) with a very big refresh cycle (something like 100~500 ms) so I can experiment and understand better.

[bitslice]

Sorry, that wasn't really clear. Yes, I'm talking about buffering the address lines.

I'm not really into dynamic ram yet, I still try to understand all the ins and outs of the refreshing. I wish I could find a small dram chip (something like 256 bytes) with a very big refresh cycle (something like 100~500 ms) so I can experiment and understand better.

You probably don't need to latch the address lines, so a 74LS244 would be OK, and maybe a 74LS245 for the data lines.

A pity the Z80 didn't anticipate larger DRAMs, then they might have included an 8 bit refresh and made everything easier.
It doesn't help that everyone's specs are different, or that the later ones switched to cas before ras

this is a pretty detailed look at it
http://www.piclist.com/techref/mem/dram/olmstead.html

[Bendba]

Thanks for the useful informations.

That would be the sort of web page I've been looking for the last three months.
Just gotta get reading, find an old ram chip to experiment with and get experimenting.
Would you have any advise of a suitable dram chip for slow clock rate (say < .5 mHz) so I can use the cheap usb logic analyzer (I know, cheap gears are not great to learn with but that's all I can get for now) to help my understanding and/our debugging before I go full speed?

Thanks again

[bitslice]

The refresh rate for drams normally spec'd at 64ms, [correction, 2-4ms] I don't think there's been a requirement for slower rates or a slower discharge.

You could in theory keep a group of cells active just by reading them continuously and rewriting the data back to them.
Nobody does this because it's just easier to refresh them normally, but its a quirk that may be interesting.

[David Hess]

You guys figured it out and answered all of the questions before I could get here.

You could in theory keep a group of cells active just by reading them continuously and rewriting the data back to them.
Nobody does this because it's just easier to refresh them normally, but its a quirk that may be interesting.

Some low cost systems did exactly this to avoid the cost of extra hardware to manage DRAM refresh; either by design they accessed all rows of memory or they used a periodic interrupt to trigger a service routine which handled it.  The original IBM PC used the 8253's timer 1 to trigger DMA channel 0 which refreshed DRAM memory.

I have heard complaints before about the Z80's multiplexed external bus.  On one hand, multiplexing means extra external hardware for demultiplexing.  On the other hand, it means a less expensive package because it has fewer pins.

[westfw]

The refresh rate for drams normally spec'd at 64ms

In the Z80 era, the required refresh rates for DRAMs were typically about 2ms.  (4116 and 4164 are "typical" part numbers from those days.  41256 increased the time to 4ms, but that was a 68k-era RAM chip...)  (SUN-1 CPU boards did their refresh in software.  Every 4ms there was an NMI interrupt, and the ISR would do the required number of consecutive nops to access each row...)

[obiwanjacobi]

Yup, been there done that.

Note that the Refresh only occurs at the second half of the first Machine Cycle (M1 is low). If an instruction has additional bytes to read (LD A, n for instance) those extra bytes do NOT produce Refresh signals. Prefix bytes (DD, FD, CB etc) are also M1 cycles.

So when you run any program, an irregular pattern occurs of when the Refresh signals (M1 cycles) appear...

[2c]