EEVblog Electronics Community Forum
Electronics => Projects, Designs, and Technical Stuff => Topic started by: XaviPacheco on June 14, 2018, 03:13:36 am
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Hi,
Normally, gate resistors are low values around 1-100 ohms. I've seen that they also have low power ratings. How is the power rating determined? I mean, let's say that the gate voltage is 12V, and I want to limit the gate driver peak current to 2A. Of course, 2A with a low resistor throws a high power rating. But 2A is not necessarily the needed gate current, it is just limiting the driver current just in case. But the point is that the peak current is an instantaneus value to charge the gate capacitance. So we are talking about peak power rating. My question is, how can low power rating resistors stand high "peak" wattages? I'm kind of confused trying to understand this.
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There are some failure modes (ie resistance change) with applying pulse current to some types of resistor (IIRC thick film is generally worse than thin film). You can buy pulse-rated resistors so if you're worried about it, choose one that is rated for the peak power dissipation you're putting through it.
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Gate capacitance itself is a "short circuit", it takes whatever current it can, limited by all resistances in the system.
You are charging a capacitance through the combination of:
* driver output resistance
* your Rg
* FETs gate resistance.
Fortunately, all of these are almost always defined in the datasheets.
Initially, when the FET is fully on or off, it's equivalent total gate capacitance is charged to the full voltage differential of your gate drive supply. So, for a typical imaginary example, the peak current would be:
I = U/R = Usupply/(Rdrv + Rg + Rfet) = 10V/(3 ohm + 4.7 ohm + 2 ohm) = 1.0A.
Now, the current has a decaying shape, because the voltage at the gate rises and hence, the voltage over the current-limiting resistances drops.
Let's again calculate for a FET with Qgs(pre-threshold) = 5 nC and Qgtot (at Vgs=10V) = 30 nC. (Typical size to be driven with 2A drivers in a high frequency switching application.)
At 1.0A, each nanosecond provides 1 nC to the gate. Let's slice it down with each slice being constant current, it may be easier to think than the decay curve. So, after 5ns, we have charged the gate to the threshold voltage, let's say typically 3V.
Slice 1: 1.0A for 5ns
Now, the gate is at 3V, the channel is slightly conducting and the gate sees the full capacitance, which slows gate charging down. Current at the start of this slice is:
I = (10V-3V)/(3 ohm + 4.7 ohm + 2 ohm) = 0.7A.
Gate is charged at 5 nC, so 25 nC left to charge it totally to 10V. Let's take a bigger slice now, let's charge 50% of the remaining charge (12.5nC). At 0.7A, each nanosecond charges 0.7 nC. To get 12.5nC, we need 18 ns.
Slice 2: 0.7A for 18ns
Now, the gate is at about (10V-3V)/2+3V (halfway charged after the threshold) = 6.5V. The current is:
I = (10V-6.5V)/(3 ohm + 4.7 ohm + 2 ohm) = 0.36A.
Let's call that slice 3 and; at 0.36A, charging the remaining 12.5nC takes 35 ns
Slice 3: 0.36A for 35ns.
Then, let's say our switching frequency is 200kHz, which means half period of 2500 ns. No gate current until the next switching event. So:
Slice 4: 0A for 2442ns
So now we can look at the power dissipation in our 4.7ohm gate resistor:
Slice 1: 1.0A for 5ns: P=I^2R = 1.0^2*4.7=4.7W
Slice 2: 0.7A for 18ns: P =2.3W
Slice 3: 0.36A for 35ns: P = 0.6W
Slice 4: 0A for 2442ns: P = 0W
The average power is 5/2500*4.7W + 18/2500*2.3W + 35/2500*0.6W = 0.034W. So let's pick a 0603 resistor.
Now, let's open up a datasheet for a typical 0603 chip resistor. Oh wait, the resistor manufacturers don't bother providing the highly relevant pulse handling data in their datasheets, even though there parts are used in billions and billions every day. Instead, the designer needs to google for some "typical", similar enough product (if your resistor is thin film, google for thin film!) that has this property tested. It turns out, this property is very seldom tested, unless they sell a super expensive product that has gone through this characterization.
https://www.vishay.com/docs/28705/mcx0x0xpro.pdf (https://www.vishay.com/docs/28705/mcx0x0xpro.pdf) page 6 continuous pulses is the closest you'll get. Continuous pulse specification without a specified duty cycle can sound weird, but the idea is that if you limit the average power dissipation at the specified maximum, you can then follow this curve.
Now let's see... 4.7W for 5 ns. This is the upper limit of peak power dissipation, but the resistor would be OK for 200 microseconds, i.e., 40000 times longer!
2.3W for 18 ns. The resistor would be OK for two freaking milliseconds.
... yeah.
As you can see, the curve "saturates" at about 4.7W. You are allowed to dissipate 4.7W for 200us no problem, but apparently aren't allowed to dissipate any more for even 1 picosecond. It's your call to evaluate whether this is based on any physical fact or if they just wanted to give some hard limit for you.
Blown gate resistors are fairly rare. Of course, if you try to use a 0201 part as a gate resistor for some kilowatt-switching huge FET bank or IGBT, it's not gonna survive. But generally, resistors handle handle peak power quite well.
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Well, there's a much easier way to arrive at that answer -- use an energy argument, and if you like, prove it with a little calculus. I'll leave the latter as an exercise for the student, so the former:
- For a linear capacitance and resistance, and a step voltage source, the RC circuit dissipates half the energy as power in the resistor, and half as charge stored in the capacitor.
The argument works the same as the "charge is conserved, but what happens to the energy when you discharge one capacitor into another?" situation: it doesn't matter how it got there, just that it did, in a lossy (nonconservative) way.
So, for a gate of Vgs(on) = 10V, Qg(tot) = 100nC, and Fsw = 100kHz, we have P = Vgs(on) * Qg(tot) * Fsw = 0.1W. Simple as that. All just ratios multiplied together, and the constant is 1 (dimensional analysis wins again!).
- For a nonlinear capacitor, we cheat: use an equivalent capacitance. Now it matters how the capacitance is distributed, over time or voltage; but as long as it happens in a similar way each time, we can use an average or equivalent figure.
This is why we use the Qg parameter, NOT the Cgs parameter -- that's a small-signal, off-state parameter, useless to switching circuits.
- For a non-ideal step, losses are lower.
That is, for a real circuit, rise time will NOT be zero, and that means the cap doesn't look like a "dead short" (absolutely nothing, at AC, is a "dead short" anyway, not even superconductors -- especially not!). So the energy will be dropped less than half and half, between resistance and capacitance. In the extreme, a very slow input develops ~0 current through the resistor (I = C * dV/dt!), and therefore dissipates ~no loss in it.
Which is also just to say: an R+C network is a lossy capacitor, depending on frequency. It approaches an ideal capacitor as frequency goes down. That's all.
In real circuits, a near-50% figure is, at the very least, a safe overestimate, and you can expect to get very close to this, most of the time.
Also in real circuits, the driver is almost always a lossy amplifier, not a resonant converter -- this actually guarantees >50% losses, i.e., the driver dissipates more real power than reactive power delivered to the capacitor. Making it a very good estimate indeed. :)
(You can contrive circuits with lower gate drive losses -- use a series inductor and clamp diodes to get quasi-resonant gate drive, for example. The downside is greater complexity for not much power savings, and a significant reduction in Fsw because switching speed is now limited by a fraction of internal gate resistance, rather than the full figure.)
Tim
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- For a linear capacitance and resistance, and a step voltage source, the RC circuit dissipates half the energy as power in the resistor, and half as charge stored in the capacitor.
Exactly. That's why in my previous post, I didn't apply the 0.5 factor as seen in E=0.5*CV2.
Or -- if you prefer to think of it in those terms -- it's still correct, it's just that you burn it twice per cycle, so you have 2 * 0.5. :D
Tim
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I know i am bringing up very old topic, but highly relevant to it.
Seems i faced situation when my inexperience caused burning of gate resistor.
Circuit is: Boost converter, single FET, undersized inductance (means high RMS and duty cycle, there is losses in inductor core, but its another thing), undersized wrong resistor on gate (0603 thick film, JLCPCB "basic" library UNI-ROYAL(Uniroyal Elec) 0603WAF200KT5E) 2ohm, 4A driver driven by 12V.
Mosfet: nthl082n65s3f with fairly large Ciss 3410pf
Inductor: 33uH
Input voltage about 110V Output voltage about 180V, load is up to 5A
After while, on high duty cycle, resistor burns and magic smoke escape.
I suspect peak currents are too high for this gate resistor. Maybe miller effect add something.
Did anybody faced similar issue?
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Peak currents don't matter much on the sub-microsecond scale. Your Qg ~ 80nC, at 12V, whatever frequency, and the ~0.1W rating of the resistor, is most likely what does it.
Tim
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A rule of thumb i use is 0805 for anything from D2PAK/TO220 and up. Smaller things only get 0805 if it's already on a feeder or something like that. There was maybe one instance where It went wrong, and it was a rather extreme situation (8ph, 5V / 200A nominal, DSP controlled), used double MOSFETs for every phase.
As for the peak current rated resistors, this gets really relevant at much much huger power levels.
At lower power levels the problem arises from usual thick- and thin-film laser trimmed resistors having hotspots that later become failure points. The best resistors for pulsed power rating are bulk material resistors, but that is 5W+ THT part territory. (Most resistors have some resistive film / wire wrapped around ceramic core). After those wire wound are the next best thing, although is not selected properly really suck at higher frequencies due to parasitic inductance.
We had a design, where we had to short a REALLY HIGH power source (Think 400V mains at about 200A) through a resistor for a few miliseconds, after which it was being cooled down for some longer time. The biggest problems are thermal expansion and thermal impedance (as in time related thermal flow) and any COTS resistor, even really exotic ones would fail and /or literally crumble to dust. Ended having to design and manufacture our own resistor.
Power industry T&M gear is fun sometimes :)