The thing is, I did spend a lot of time researching circuits to measure dynamic saturation Vds. And my conclusion is that there is nothing really good out there, bad linearity around 0, high offsets.... Since many rely on limiting resistors to the diodes then the higher the VDS voltage the slower the response time. Most of them have a settling time around 10us which is too slow and undervoltage swings are typical (as seen in the OP traces), this problem getting worse the faster the dV/dt of the negative going Vds.
So eventually I did design something different, attached is a measurement done with this circuit of mine, sorry can't post it because it will become a product soon.
CH2 is a 200V rail being switched to 0 with a mercury relay, measured with a x100 passive probe.
CH3 is the saturation voltage 1:1 scale, starting at 15V.
CH3 is again measured in the next graph alone, without CH2 as I tested that the x100 probe did affect the measurement.
The settling time is less than 100ns, and there is no negative going peak given the fast decay of the Vds. This is the kind of speed needed in todays fast inverters that have <1us ON time.
The linearity is tested with a triangle wave around 0, but I don't have any graphs at hand. Also there will be a x10 times output for devices that have very low saturation Vds.