I've got a project that calls for a 10/20/40* MHz single-ended clock and a 180 MHz differential clock. Now because I'm the type of fool that will spend a month looking for a one-day workaround to a one-week task, I've been playing around with Analog Device's ADIsimCLK software and TI's Webench Clock Designer website. My experience has been very poor in comparison with TI's Webench Power Designer site, here are the things I am sad about:
- The suggested designs invoke vastly capable chips (
example) with 1-3 GHz VCOs, multiple outputs, and all sorts of other features. Question: is it standard practice, like with microcontrollers, to use clock generator parts with vastly more capability than you require? Is it standard to stop off at 1.62 GHz on the way from 40 MHz to 180 MHz? Or are these tools hiding much simpler solutions from me?
- The simulators provide very specific simulation, even time-domain transient simulations. And yet when I look at the datasheets of the parts, I see pages and pages of configuration registers that the design tools fail to provide any clue how to set. I'm talking weird stuff beyond your normal divider and fractional registers -- stuff like antibacklash pulse width, VCO calibration registers, etc. Now I know that I'm being lazy to an extent here, but this makes no sense: either these registers are critical to the performance of the part (in which case surely the simulator should divulge the settings that it's using in the simulation), or the registers are immaterial (in which case, why are they even there?)
I guess my question is, should I harden up and forge ahead with these super-parts? Or am I missing a far easier path here?
* By "10/20/40", I mean that I don't care whether it's 10 or 20 or 40, whatever works out best. (Ironically the PLL inside my MCU is very easy to use for taking any of 10 or 20 or 40 up to 40 MHz!)