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Multi-plexer-plexer for 16.3 Kbps communication
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Rora:
I'm designing an array of reader contacts for 1-wire ID buttons. I'll be using the new T.I. TMUX1108 8:1 multiplexers due to its excellent RON, leakage, and off/crosstalk isolation--it meets or exceeds the performance of the 1-Wire OEM chips designed for the same purpose.

I'd like to follow a pattern of using 8 of these with the A0, A1, A2 inputs in parallel across all 8. The enable pin would then be multiplexed by a 9th. This would allow, say, 011 to select S3 on all 8 multiplexers, then cycle through the enables for each with the 9th multiplexer to read all the S3s in order.

The communication through the multiplexer will be 16.3 Kbps 1-Wire TTL with a bus master that has advanced slew control and A/D filtering, so I expect it should work pretty reliably... that's why I need someone to tell me why this is a bad idea. :-BROKE
Kleinstein:
The principle idea to combine 8 MUX chips is OK.  For just logic signals, one may not need so low an R_on and very low leakage. Just normal 74HC(t)4051 (74LV4051 for less capacitance) should be sufficient.
The more critical parameter than R_on may be the capacitance (some 60 pF at the common pin of the TMUX1108, 24 pF for the LV4051).
8 of these chips would add up quite a bit.

However for the control of the enable pins, I would not use an analog MUX chip, but a logic gate decoder.
The function is similar, but no extra pull down / pull up needed.  One has to check polarity - something like 74HC138 should work.

Alternatively one could keep the enable pins all active and use a 9th MUX as a second stage, choosing one of the outputs from the 8 chips of the 1 st. stage. This would reduce the capacitance, as only 2 chips would contribute.
Rora:

--- Quote from: Kleinstein on August 30, 2019, 06:22:37 am ---The more critical parameter than R_on may be the capacitance (some 60 pF at the common pin of the TMUX1108, 24 pF for the LV4051).
8 of these chips would add up quite a bit.

...

Alternatively one could keep the enable pins all active and use a 9th MUX as a second stage, choosing one of the outputs from the 8 chips of the 1 st. stage. This would reduce the capacitance, as only 2 chips would contribute.

--- End quote ---

This idea makes the most sense, this way all signal lines are not sharing any contacts. Would also allow me to place the pull-ups on the 8 individual signal commons which would keep the downstream 1-wire device charged until it is switched onto the main common, instead of on all 64 signal lines. Would just need to program in a short wait when switching the 8 muxes to a new set of sources.
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