I'm designing an array of reader contacts for 1-wire ID buttons. I'll be using the new T.I. TMUX1108 8:1 multiplexers due to its excellent R
ON, leakage, and off/crosstalk isolation--it meets or exceeds the performance of the 1-Wire OEM chips designed for the same purpose.
I'd like to follow a pattern of using 8 of these with the A0, A1, A2 inputs in parallel across all 8. The enable pin would then be multiplexed by a 9th. This would allow, say, 011 to select S3 on all 8 multiplexers, then cycle through the enables for each with the 9th multiplexer to read all the S3s in order.
The communication through the multiplexer will be 16.3 Kbps 1-Wire TTL with a bus master that has advanced slew control and A/D filtering, so I expect it should work pretty reliably... that's why I need someone to tell me why this is a bad idea.
