Please see the attached data sheet - CD4538 CMOS monostable.
Data sheet claims ide pulse width range,
Wide pulse-width range 1 ms to infinity
Further it states on page 4 under Operating Conditions minimum timing resistance value of 5K whilest maximum value is not specified , how ever it is limited by a clause which explains:
"...The maximum usable resistance R X is a function of the leakage of the Capacitor C X , leakage of the CD4538B, and leakage due to board layout, surface resistance, etc. ..."
At the same time Cx is not defined at all.
What maximum pulse width might be reasonably and repeatably achieved using current technology tantalum capacitors as part of timing circuit?