EEVblog Electronics Community Forum
Electronics => Projects, Designs, and Technical Stuff => Topic started by: ChuckMuz on April 24, 2022, 04:15:58 pm
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I found this interesting tidbit:
Abstract:
The effectiveness of using the parallel combination of large-value and small-value capacitors to increase the frequency coverage of either one and overcome the effect of lead inductance is examined. Computed and experimental results are given that show this scheme is not significantly effective. The improvement at high frequencies is at most 6 dB over the use of only the large-value capacitance.
https://ieeexplore.ieee.org/document/135626?reload=true&arnumber=135626&isnumber=3696&punumber=15&k2dockey=135626%40ieeejrns&query=%28%28effectiveness+of+multiple+decoupling+capacitors%29%3Cin%3Emetadata%29&pos=0 (https://ieeexplore.ieee.org/document/135626?reload=true&arnumber=135626&isnumber=3696&punumber=15&k2dockey=135626%40ieeejrns&query=%28%28effectiveness+of+multiple+decoupling+capacitors%29%3Cin%3Emetadata%29&pos=0)
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6 dB is not nothing, and in some designs it provides enough of improvement. But more importantly, having provisions to add parallel capacitor is better than re-spinning the board.
Also, the article is from 1992, a lot has changed since then in capacitor technology and IC technology.
There are more recent articles on the same subject, but it does not look like there is a single right answer.
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In 1992 thru hole parts were good for almost everything. Not these days when extremely fast signals are present in cheap consumer equipment. Also what matters more is package size of the capacitor, rather than capacitance when adding multiple capacitors in parallel.
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6 dB is not nothing, and in some designs it provides enough of improvement. But more importantly, having provisions to add parallel capacitor is better than re-spinning the board.
Also, the article is from 1992, a lot has changed since then in capacitor technology and IC technology.
There are more recent articles on the same subject, but it does not look like there is a single right answer.
Yup. 6 dB is not nothing. 6 dB is half the amplitude.
In particular, one major point regarding the parasitic inductive component in capacitors depends a lot on both its internal construction AND its leads, one reason that the big electrolytic, through-hole capacitors are a very poor choice for decoupling. But even with the SMD ones, there's a definite difference compared to SMD ceramic caps for instance. The parasitic series resistance is even more telling. No way you can get as low in electrolytic caps than in ceramic ones.
The value of the capacitance matters to some degree of course - the larger the capacitance, the larger the cap and its internal structure, and usually the larger the series resistance and inductance, but the technology often matters more. Just compare the typical series resistance and inductance of, say, a typical 10µF ceramic, and 10µF electrolytic cap, and see for yourself.
Both series resistance and inductance have a negative impact on decoupling.
Now, given the difference of those in two typical SMD ceramic caps, paralleling, for instance, a 10µF ceramic with a 100nF ceramic is mostly useless.
But there's of course not just the caps' characteristics themselves, but merely their physical size. You will not be able to place a big cap close enough to power supply pins of an IC, and trace length will also significantly hinder decoupling. So using smaller caps (thus, much smaller capacitance) very close to IC pins is always better. Something you can't measure if you don't take PCB routing into account.
In any case, putting decoupling caps too far away from what they're meant to decouple is a bad idea and doesn't work well. So, paralleling a large cap with a small one, both placed far away from the circuit they are meant to decouple won't indeed make a whole lot of sense.
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Since 1970s good engineering practice and worst case designs use a lytic or tant 1..47 uF and a monolithic céramique 1..100 nF to,bypass the entire board or,even for an individual IC.
Jon
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Since 1970s good engineering practice and worst case designs use a lytic or tant 1..47 uF and a monolithic céramique 1..100 nF to,bypass the entire board or,even for an individual IC.
Jon
This is the way. TL;DR:
- 10uF or larger electrolytic (Al/Ta) or damped ceramic as bulk capacitance for the rail. Location isn't important.
- Pick the smallest ceramic case size you're willing to deal with
- Pick the largest capacitance you're willing to pay for in that case size
- Put those as close as possible to the IC pins (=lowest inductance connection realistically feasible)
- Don't bother with parallel capacitor shenanigans unless you've actually done analysis for this particular case.
- If you truly need more capacitance (e.g., SMPS filters), put any bigger capacitors farther away (but still close!), but do not compromise the position of the physically small capacitor
Follow that list and you will do better than 95% of app notes out there. And it will work, and you will pass EMC. (Or at least have a shot at it, this doesn't magically fix the rest of the design....)
The reason this works is that bypass capacitor performance is really limited by ESL. People think ESL increases with increasing capacitance, but it doesn't. It actually mainly scales with package size and geometry. (But capacitance and package size are related, particularly with older parts, hence the myth.) So control the package size and you are free to add as much capacitance as you can. For bypass applications, more capacitance is always a good thing.