### Author Topic: Multislope Design  (Read 85547 times)

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#### iMo

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##### Re: Multislope Design
« Reply #75 on: January 03, 2019, 08:34:34 pm »
PF2019!
I've been trying to understand how the multislope works. Because of lack of parts I've done a simple simulation for the run-up phase. My understanding so far is following (an Example only):
1. I created 1000 chunks, 20us each, such it fits into 20ms
2. after resetting the integration Cap the logic is switching the VrefP and VrefN based on the comparator's output such it tracks the integrator around the zero (at 20us comp_output sampling period)
3. The binary counter (the top pane green indicator) shows the number of crossings through zero.

With 0V input I get something like 470 counts (runup zero crossings), With +10V and -10V I get ~250counts. The counts to input voltage dependency is V shaped therefore. Is that something I may expect or I miss something fundamental here?
« Last Edit: January 03, 2019, 08:57:47 pm by imo »

#### Kleinstein

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##### Re: Multislope Design
« Reply #76 on: January 03, 2019, 09:07:39 pm »
The simulation is about what one should expect - at least at the very basic level. To get better accuracy there should be extra provisions to keep the number of switching events constant.

In a simple (though good) case the ref switches follow a sequence where the reference is
1)  fixed positive
2) positive or negative depending on 1 comparator reading
3) fixed negative
4) positive or negative depending on 1 comparator reading

The relevant number is not counting zero crossings, but the time the references are active (e.g. counting positive phased for step 2 and 4 in the example above).

#### iMo

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##### Re: Multislope Design
« Reply #77 on: January 03, 2019, 10:49:39 pm »

By replacing a piece of wire I've been now counting the positive charge. My chunk of charge is 20us*I_ref and the total number of chunks is 1000 (=20ms).
With
Code: [Select]
10V inp I get  2500V  inp I get  501-10V inp I get 749Looks much better
Thanks!

#### iMo

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##### Re: Multislope Design
« Reply #78 on: January 08, 2019, 01:04:19 pm »
..To get better accuracy there should be extra provisions to keep the number of switching events constant..
I think this scheme (a pwm like modulation) would be something you refer to.
The Vcomp transition from 1 to 0 - that is something I cope with. When compared to zero I get usually problems - Vintegr moves somewhere off for reasonable Ri,p,n, Tx and C values and when sweeping from -10 to 10V Vinp.
« Last Edit: January 08, 2019, 01:57:34 pm by imo »

#### Kleinstein

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##### Re: Multislope Design
« Reply #79 on: January 08, 2019, 02:07:37 pm »
There are different possible schemes to get a constant number of switching events. The picture seems to have used a continuous PWM like sequence. It looks like 1 transition is simply by time. The other maybe from the zero crossing of the integrator with some delay.

How, and how accurate this is done during the run-up is not important, as the errors don't add up. A more crude or noisy control would only increase the excursions of the integrator a little. This can effect the average voltage of the integrator and thus the effect of dielectric absorption. However normally the modulation frequency is high enough (e.g. > 10 kHz) to not make his an issue even with a simple control scheme.

During run-up it's important to sum up the correct times for the references - so the reference switches should be in sync with a clock and not directly driven from the comparator.

The scheme I had described is a little different, with no fixed transitions, but fixed states.  Each Cycle has only 4 possible sequences, 1 dominant positive one dominant negative and 2 mixed, half and half. This corresponds to 2 readings taken from the comparator.
The continuous PWM way can have a slight advantage, but is more difficult to implement. The for step case is more like simple.

#### iMo

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##### Re: Multislope Design
« Reply #80 on: January 08, 2019, 04:15:15 pm »
..The scheme I had described is a little different, with no fixed transitions, but fixed states.  Each Cycle has only 4 possible sequences, 1 dominant positive one dominant negative and 2 mixed, half and half. This corresponds to 2 readings taken from the comparator..
Could you point us to a simple picture with the cycle, plz?

#### Kleinstein

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##### Re: Multislope Design
« Reply #81 on: January 08, 2019, 04:42:42 pm »
The modulation scheme I described is from the US5200752  patent.

In short form this a 4 step cycle:
1.  fixed reference at positive for a short time (e.g. 2 µs) and read the comparator at the integrator output
2. depending on the comparator reading before chose positive or negative reference for a fixed time (e.g. 20 µs)
3.  like step 1, but with negative reference
4.  like step 2

The reference setting is changing from pos to neg either between steps 1 and 2 or between  2 and 3 .
The reference setting is changing from neg to pos either between steps 3 and 4 or between  4 and 1 .

Attached is a simulated (spread sheet) curve. The blocks mark the beginning of the steps mentioned above. The rundown phase has the steps in short sequence.

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#### iMo

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##### Re: Multislope Design
« Reply #82 on: January 09, 2019, 12:52:37 pm »
Your scheme solves the issue with none-constant number of P and N switching. But the number of constant duration P and N phases is discrete and rather low, therefore the "runup resolution" is low (you count the number of those discrete phases).

My scheme above with "continuous pwm" during the runup has constant number of switching, and, the P/N is none-discrete in each sample period.
When the P or N "on" time will gate a 50MHz oscillator (an example) and will count its clock I may get for example 450000/450000 counts with Vin=0V and with 50us sampling period in the 20ms integration time frame (and maybe 50000/850000 with 10V, etc.)..
« Last Edit: January 09, 2019, 01:02:05 pm by imo »

#### Kleinstein

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##### Re: Multislope Design
« Reply #83 on: January 09, 2019, 04:20:37 pm »
I know that the run-up resolution is limited. However in my view resolution is not the important point for the run-up phase. The first important point is the worst case charge at the end of run-up, which influences the length of the rundown phase. A second, related point is the needed integration capacitance which corresponds to the worst case charge in between. A smaller capacitance might lead to less noise for short integration times.  For short integration times the noise is often limited by higher frequency noise of the integrator and amplifier behind, and this gets better with a smaller capacitor.

However to longer integration times the integrated low frequency noise takes over. So there is a limited use in reducing the capacitance very much.  Depending on the details of the integrator and rest of the circuit something like < 1-10 nF for the cap would be nice to have the cross over at less than 20 ms. A smaller cap could still help with very fast conversions, but it also needs a faster amplifier in the integrator.

The continuous PWM type feedback can give a lower charge if the control is well made. Something like a factor of about 2 for the maximum charge and a little more (with a BW limited input signal) for the final charge. However the simple feedback directly from the comparator and a fixed time for the other transition (this is similar to the Adcmt 6581 DMM) is not really better than the simple 4 phase system. I think the 2 methods are about equal quality and similar effort. It would need a more advanced PWM feedback (e.g. using a fast ADC or the comparator timing) to get the slight advantage.

There is absolutely no need to use a very fast clock during run-up. It not about fine steps, but knowing the steps well.  So 10 µs steps are fine as long as the length is accurate (e.g.  to some 0.1-1 ns).  It only adds about 1 time step to the rundown time, that usually is more in the 100-500 µs range anyway. The main resolution comes from rundown. Here higher clock can help - though there are limits to how fast the comparator is or should be.

#### iMo

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##### Re: Multislope Design
« Reply #84 on: January 09, 2019, 04:59:15 pm »
The "continuous pwm" in my picture is intended for runup only. The worst case residual charge for run-down will be -10 or +10V.
The run-down will be the next process and a business as usual.

Imagine a simple DIY ADC with following spec:

1. run-up phase duration 20ms (50Hz suppression)
2. number of fixed steps in the run-up is 1000, each step is 20us
3. each runup step starts with VrefP (P) "on" and it is "PWM", where P/N ratio varies inside the step (in my picture the step is the period between T1 and T2 for example)
4. the number of P and N switchings in the runup is constant
5. total runup charge measurement: when the Vref P or N is active ("on"), it gates a "P" or "N" 20bits long binary counter, and the counter counts a 50MHz clock -> that way it measures the total runup P and N duration (the charge) with a 20ns resolution (1 million total counts in 20ms)
6. after the 20ms runup finishes the run-down phase starts, with whatever strategy you want (ie 16-20bit fast SAR as a "residue ADC", multislope, or other known approaches)
7. the run-down phase duration max 19ms
8. max ADC measurements per second: 25

With Ri, Rp, Rn around 20-50k and the integration cap=3n3-6n8 you may fit inside the 20us runup steps.

The resolution of runup:     16+ bits
The resolution of rundown: 14+ bits.

« Last Edit: January 09, 2019, 08:00:01 pm by imo »

#### Kleinstein

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##### Re: Multislope Design
« Reply #85 on: January 09, 2019, 08:32:04 pm »
For the run-up resolution the counter clock is not relevant. The step size to set the resolution is the time it needs to get the worst case residual charge. So if the runup is using time intervals of 10 µs to set the references, the step size is usually this time. So the resolution is more like 20 ms / 10 µs = 2000 steps  or some 11 Bits.
For the rundown the resolution depends on the method used.  In the simple case of a single speed rundown with a comparator the resolution could be something like 10 µs  (the step size from the run-up) divided by the timing resolution (e.g. 50 ns with a 20 MHz clock). So the simple rundown would than have some 10 µs / 50 ns = 200 Steps  (near 8 bit). So in total it would be near 19 Bits (plus sign).

Here it is not really relevant what accuracy the run-up has - the total resolution til after the fast rundown is integration time (minus fixed part) divided by the timing resolution for the rundown. So something like 20 ms / 50 ns = 400,000 steps.  A different value for the run-up steps only moves resolution between the 2 phases. Longer Integration would give higher resolution. The timing resolution is limited by the comparator, not just the clock.

A way to higher resolution in a slower slope to get a higher resolution without a super fast and thus high bandwidth and thus higher noise comparator.  A 2 nd slope lower by a factor of 16  could add another 4 bits. A 50 ns timing resolution is already quite optimistic for the fast slope and even more for the slower slope(s).  The BW and thus timing resolution may need to be a compromise between a short rundown and low noise. So the gain in actual resolution from the slower slope(s) can be lower, as the slower slopes may need a reduced BW.

If a residue ADC is used, its useful resolution is limited, as the scale factor depends on the integrating capacitor and absolute value of the resistors. So the gain uncertainty can limit the useful resolution, depending on how and when the scale factor is calibrated.

The time for the rundown phase in the typical better DMMs is more like 100 µs - 2 ms, usually no need for more time. This time also includes a zero phase to discharge the integrator. So with 20 ms integration there can be something like 48-49 readings per second or with an auto zero mode some 24 readings per second. Many DMMs also need more than 20 ms for there full resolution, though it can help against 1/f noise to only use 20 ms. So the resolution at 20 ms can be a relevant target, even though the full resolution might still need averaging of several of those short readings.

#### iMo

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##### Re: Multislope Design
« Reply #86 on: January 09, 2019, 09:00:25 pm »
Thus do you say that knowing the charge budget coming from references during the run-up phase with, say, 100x better resolution, plays no role?
« Last Edit: January 09, 2019, 09:30:56 pm by imo »

#### Kleinstein

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##### Re: Multislope Design
« Reply #87 on: January 10, 2019, 07:19:22 am »
One still has to know the charge budget during run-up very accurate, but one does not need a fine resolution setting the charge. So10 µs quantization is good enough, if those steps are know to something like 0.1 ns.

A coarse quantization only effects the time needed for the rundown phase and indirectly the required size of the integration capacitor.

#### iMo

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##### Re: Multislope Design
« Reply #88 on: January 10, 2019, 08:17:38 am »
Assuming "ideal" components (switches, references, comparator, integrator) and ideal precision/accuracy with any timings in runup (talking here runup only), and having two results from runup (in both cases the runup is 20ms long and all components are identical):

A. Pcharge/Ncharge = 674/326

B. Pcharge/Ncharge = 67443/32557

From what you wrote above the B has none benefit (compared to A) for the final result?
« Last Edit: January 10, 2019, 08:21:20 am by imo »

#### Kleinstein

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##### Re: Multislope Design
« Reply #89 on: January 10, 2019, 05:01:54 pm »
Just the higher resolution of the numbers has no direct benefit, as it is not about resolution, but accuracy of the actual time.

A finer quantization during run-up can have a slight advantage in getting a slightly lower final charge, if the feedback algorithm is good. But it's more about the algorithm not the quantization. A lower charge would allow a slightly faster rundown.

If done in a good way the continuous feedback could have an advantage that it could get away with a slower (AFAIK up to factor of 2) modulation.  So I am still open to a better feedback alternative.

Maybe I have a look at the continuous feedback option again - not for more resolution, but to avoid coincidence of zero crossing and reference switching.  My standing here so far is that the simple fixed time + comparator (like ADCMT6581) way is likely not better than the simple step way and the better feedback I have in mind is a little slow and needs scary complicated ASM software.

#### iMo

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##### Re: Multislope Design
« Reply #90 on: January 11, 2019, 08:39:29 pm »
Here is a complete simulation of a Run-Up phase of a simple DIY Multislope integrating ADC built from junkbox parts. Intended for people who want to play with something more complex than blinking an LED and who want to learn.

The Runup is 20ms long, with 1000 fixed steps @20us.
The integrator is composite one, with slope amplifier and fast comparator.
There are also 3 counters - for VrefP, VrefN and Runup_Clk events.

In the below example the input voltage is a sine wave 4Vpp, at 4V DC.
The simulation itself runs till 20ms, exactly.
You may measure the residual voltage at the end of Runup phase therefore.

The sequences and timings are provided by various voltage sources and by a simple CMOS logic. Timing is considered precise.

The ADC strategy is to sample the comparator output @20us periods, and to switch the VrefP and VrefN references as required. The number of VrefP and VrefN switchings is not constant, but 1000 in total.

This is not a continuous pwm Runup, nor any high-end related stuff, but rather a wiki-like one example intended for hobby experimenters.

With the below ready example you should get VrefP=321 and VrefN=679 at the runup end. With Vinput=4V with no added sine wave you should get the same (as the 500Hz sine wave cancels out during integration).

With a -10V Vinput you may get VrefP=955 and VrefN=45, and vice versa with 10V at its input.

With Vinput=0V (input shorted) you should get VrefP=504 and VrefN=496.

The 3 voltages in the upper pane do represent the event counters, at the end of the simulation you may go with the cursors to the very end of the timescale and read out the counters and residual voltage values.

Enclosed is the .asc source and .plt file.
Worked with LTspice latest, and the Bordodynov library for some parts used. The parts were chosen as an example only. You may experiment with better parts when models are available.

Note:
1. Before you start to mess with different parts, R/C values and timings, try to run the stuff to get familiar with it.
2. Not all models of op-amps and switches work fine. Feel free to experiment.
3. The V1 schematics is rather complex, the simulation speed is about 30us/sec with a mainstream 2 core notebook. So take a nap.
4. You will get around 750MB of data (waveforms) with the example.

Provided as-is.

« Last Edit: January 12, 2019, 08:42:39 am by imo »

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#### Kleinstein

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##### Re: Multislope Design
« Reply #91 on: January 11, 2019, 09:23:06 pm »
It's an interesting way of simulating more digital stuff. The simulation looks valid.

However a constant number of reference switching events is kind of a requirement to get good accuracy:

I get something like 2 pC of charge injection from a pos/neg/pos cycle for the reference switches. With a reference current of some 300 µA the 2 pC correspond to an equivalent timing error of some 6 ns or some 0.3 ppm of error for a difference of 1 switching cycle. The DG419 are relatively low resistance and may thus have even more charge injection.

So I don't think the suggested feedback method would really work.
If one does not want to program in ASM one could still use an µC to control the feedback and use 2 (+1 for the input) external flipflops to synchronize the reference switching to a constant clock (e.g. 200 kHz from the µCs timer). This way slight timing errors in from the program would not matter.

#### iMo

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##### Re: Multislope Design
« Reply #92 on: January 12, 2019, 09:12:26 am »
And here is a Basic version, with minimum parts. It cannot be done simpler, afaik.
The simulation speed is about twice the above version.
Btw, I've seen an ADC in hardware (in situ), in this Basic configuration (better parts used) which claims 6.5digits.. Simple rundown phase used.

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##### Re: Multislope Design
« Reply #93 on: January 12, 2019, 09:50:39 am »
Nice topic
ASiDesigner, Stands for Application specific intelligent devices
I'm a Digital Expert from 8-bits to 64-bits

#### Kleinstein

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##### Re: Multislope Design
« Reply #94 on: January 12, 2019, 10:28:48 am »
And here is a Basic version, with minimum parts. It cannot be done simpler, afaik.
The simulation speed is about twice the above version.
Btw, I've seen an ADC in hardware (in situ), in this Basic configuration (better parts used) which claims 6.5digits.. Simple rundown phase used.

The implementation looks simple for a discrete parts solution or in the spice simulation. There are a few possible simplifications: e.g. using a single chip with 3 SPDT shwitches (e.g. 74HC4053). The logic part could also be done by a CPLD or µC. So the HW side could use less chips.
My current favorite is using a µC - a little similar to the early MS-ADCs, but with a modern faster µC in a single chip instead of a slow CPU plus support.

One can get high resolution even with a simple rundown, if the integration time is long enough. If an AZ OP is used in the integrator the useful integration time is no longer limited by 1/f noise. As an extreme the Solartron 7081 goes up to 8 digits without a slow slope, though only after some 50 seconds. The circuit is not a classical MS ADC, but more like a continuous integrating ADC.  However a classical MS ADC build in a similar way could perform similar.

Still I don't think using an AZ OP and very long integration is the modern way to go, as they are relatively noisy and with computer readout there is also value in good resolution at shorter times (e.g. 1-10 PLC).

#### iMo

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##### Re: Multislope Design
« Reply #95 on: January 12, 2019, 10:55:09 am »
.. There are a few possible simplifications: e.g. using a single chip with 3 SPDT shwitches (e.g. 74HC4053). The logic part could also be done by a CPLD or µC. So the HW side could use less chips.
My current favorite is using a µC - a little similar to the early MS-ADCs, but with a modern faster µC in a single chip instead of a slow CPU plus support..
The max voltage with 74HC4053 is +/-5V, afaik. That limits the part a bit.
I think nobody will mess with uC in the inguard logic today. A complete logic with counters and serial output (opto isolated) fits into a smallest fpga or mid cpld (iCE40, or similar). The verilog exercise is a weekend project for most today's talented builders with 6++ digits ambitions..
« Last Edit: January 12, 2019, 11:04:17 am by imo »

#### Kleinstein

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##### Re: Multislope Design
« Reply #96 on: January 12, 2019, 11:14:01 am »
If used to switch at the integrator input the +-5 supply limit of the HC4053 is not a problem. The signal switched is essentially at ground level (+- maybe 50 mV from transients) and even during turn on or errors the worst case current from a higher voltage is limited to some 0.2 - 0.5 mA.
There are some DMMs that use the HC4053: the HP34401 and the Fluke8845/6.

I know that modern designs seem to prefer CPLD or FPGA over µC. However from the noise problems a single chip µC should not be that much different from a FPGA. It kind of depends on the experience whether one prefers Verilog over hard core ASM. I personally prefer ASM -though I know it gets tricky if a 8 bit µC is no longer enough, as the faster ones tend to be not that predictable in the timing.

#### jaromir

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##### Re: Multislope Design
« Reply #97 on: January 12, 2019, 07:39:39 pm »
I made this multislope runup (+simple rundown) integrating ADC. It has full scale range +-14V, with resolution up to tens of microvolts. Least significant digit is rather stable.
Inguard control logic is in single EPM240 CPLD, configuration written in Verilog. CPLD also contains UART for sending the output results via single wire. On the second picture you can see complete setup, taking measurement of CPLD power rail. Power supply is the big block with metallic standoffs providing floating supply for ADC and blue digital board, containing optocoupler for galvanic separation from ADC and PIC18F47K40 to convert ADC counts into voltage values.

This is just feasibility study; I'm working on more refined voltmeter project at the moment.

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#### iMo

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##### Re: Multislope Design
« Reply #98 on: January 13, 2019, 01:36:02 pm »
Here is a RunUp simulation of the Basic ADC which could fit above Jaromir's POC design well (concept with typical R/C/timing values, not the identical parts and detailed schematics).

It works nice with perfect runup results (see the comments in the schematics).

The OPA134 model does not work well, therefore I've been using the LT1022A instead.

Also I have replaced my Version1/2 DG419 switches with the MAX4659 models I found in my LTspice junkbox.

The simulation speed is now 10x of the previous one.

Fyi - the ADC's Vinput=5V DC with 2Vpp 500Hz sine on it returns 150 counts .
« Last Edit: January 13, 2019, 02:16:35 pm by imo »

#### Kleinstein

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##### Re: Multislope Design
« Reply #99 on: January 13, 2019, 01:53:46 pm »
It's only a small detail and may not effect the simulation: the switch for the input signal should be wired like the reference channels.

@jaromir:
The board looks nice. I find it a little odd to have the resistor for the input to the integrator at 200 K. This is rather high impedance and twice the resistance at the references. With equal resistors one would have a smaller input range, but also better compensation of the switch resistance.

Smf