The "continuous pwm" in my picture is intended for runup only. The worst case residual charge for run-down will be -10 or +10V.

The run-down will be the next process and a business as usual.

Imagine a simple DIY ADC with following spec:

1. run-up phase duration 20ms (50Hz suppression)

2. number of fixed steps in the run-up is 1000, each step is 20us

3. each runup step starts with VrefP (P) "on" and it is "PWM", where P/N ratio varies inside the step (in my picture the step is the period between T1 and T2 for example)

4. the number of P and N switchings in the runup is constant

5. total runup charge measurement: when the Vref P or N is active ("on"), it gates a "P" or "N" 20bits long binary counter, and the counter counts a 50MHz clock -> that way it measures the total runup P and N duration (the charge) with a 20ns resolution (1 million total counts in 20ms)

6. after the 20ms runup finishes the run-down phase starts, with whatever strategy you want (ie 16-20bit fast SAR as a "residue ADC", multislope, or other known approaches)

7. the run-down phase duration max 19ms

8. max ADC measurements per second: 25

With Ri, Rp, Rn around 20-50k and the integration cap=3n3-6n8 you may fit inside the 20us runup steps.

The resolution of runup: 16+ bits

The resolution of rundown: 14+ bits.