Musing on MOSFET second breakdown

[T3sl4co1l]

This is stupid...

(But if it works, it's not stupid?...)

Suppose you take a MOSFET with relatively severe 2nd breakdown SOA limitations.  But it has pretty generous and robust avalanche ratings.  In particular, the avalanche ratings are repetitive* and thermally limited.

Suppose you have a linear application, like a hot-plugging controller, or an active voltage limiter.  Suppose you put a nice big inductor in series with the drain, and you drive it on and off hard, so that the inductor charges in saturation (Rds(on)), and discharges through avalanche.  Congratulations, you have full (avalanche mode) SOA, while still dissipating power like you would a linear device.



I mean, it probably does work, for some transistor types.  And not like there are drivers for this mode of operation, so you're rolling everything yourself to do it this way.  But imagine getting such a solution past the design review... big ol' inductor flapping in the breeze?


*Many MOSFETs have single-pulse avalanche ratings only.  There is a wear mechanism where charge can get trapped in the gate oxide, or something like that, and eventually leads to breakdown and failure.  Not all types are affected; there are some I think with less voltage across relevant gate oxide portions that still store charge but it just doesn't affect anything (as with surface passivation oxide).  I'm not aware of any way to tell between these types from datasheet ratings, aside from the repetitive specification.  And even then, the repetitive spec may be low enough energy that they're basically saying, sure it's a lifetime of a million cycles, that's good enough right?, but who cares it's 100uJ or whatever anyway.  So, beware.

Tim

[elecdonia]

Instead of allowing the flyback pulse from the inductor to be dissipated inside the MOSFET via avalanche conduction, how about adding a clamp circuit: A  diode connected from MOSFET drain to a capacitor and resistor connected to ground?

When possible I prefer to use resistors to dissipate power rather than dissipating it in semiconductor devices.

[johansen]

Could work if the hot spots created by the switching losses cause the avalanch voltage breakdown to rise, thus spreading the heat out more evenly.

From what i read the second breakdown in mosfets is caused by hot spots decreasing the gate threshold voltage and thus creating a lower on resistance channel.

The newer vertically oriented fets can still work even with half the chip blown off the board.

[T3sl4co1l]

Instead of allowing the flyback pulse from the inductor to be dissipated inside the MOSFET via avalanche conduction, how about adding a clamp circuit: A  diode connected from MOSFET drain to a capacitor and resistor connected to ground?

When possible I prefer to use resistors to dissipate power rather than dissipating it in semiconductor devices.

The application would otherwise be a linear regulator.  The power must be dissipated, either because that's the point (see also: electronic load), or because there's nowhere else for it to go.  The nearest alternative would be a buck regulator (put the inductor after the MOSFET, and add a reaction diode from GND), but a series limiter device can be used without any ground reference whatsoever (other than to sense what the output voltage is).

An RC clamp might not work because 1. the capacitor has to charge and therefore it isn't fast enough acting (of course, the series inductor causes the inverse problem, slowing the input), and 2. the resistor only has a fixed ratio of voltage to current, therefore doesn't work over a wide range, whereas avalanche works at a fixed voltage any any current, and the inductor acts to convert any input voltage and current into that output.

I have done it before where TVS diodes provide the clamping, and with much higher energy capability than any MOSFET of equivalent size.  The result is an impressive envelope in limiting mode / fault conditions.  (I designed for a 30V 20A load range, with 150ms fault duration.  A MOSFET of the same size, in linear mode (no 2nd breakdown), will hardly last 10ms doing that!)

Tim

[T3sl4co1l]

Could work if the hot spots created by the switching losses cause the avalanch voltage breakdown to rise, thus spreading the heat out more evenly.

From what i read the second breakdown in mosfets is caused by hot spots decreasing the gate threshold voltage and thus creating a lower on resistance channel.

The newer vertically oriented fets can still work even with half the chip blown off the board.

Well, VDMOS dates back to the 70s, classics like IRFxxx HEXFETs.  The verticality has only improved over time, going from a flat structure on top (horizontal gate) to diagonal (VMOS, UMOS; HEXFET is an example) to vertical (trench).  Trench has been further improved fairly recently (2000s, though I want to say it's more the 2010s since it's disseminated across all manufacturers), breaking the unfavorable Rds(on)/Vds(max) scaling that traditional devices were limited by.

This just to say, most people's experience with MOSFETs has been vertical types, so it's not clear which generation you're referring to...

I'm not sure how anything can survive on more than sheer luck with "half the chip blown off"?  Even if the die fractures in half cleanly, the exposed edge will quickly contaminate, and probably arc over if running at voltage (100s of V); local effects will probably range from apparently increased leakage to just straight up short-circuit conduction.  Especially if the crack occurs under power.  More likely the package splits open, displacing the bondwires, and arcing ensues.

(Or this comment was sarcastic, in which case enjoy the overly serious response. )

As for SOA, older types didn't have enough power density to run into 2nd breakdown, more or less; and lateral types either don't, or are prone to stability regardless (for reasons not easily explained by Vgs(th) tempco alone; though the tempco inversion point I think does fall quite low with some of these?).  Trench types are dense enough to risk 2nd breakdown, and SJ trench even moreso; it's a miracle that many don't!  In short, read the datasheet: no general conclusion applies these days.  Even some IGBTs (having even higher power density than SJ MOSFETs!) boast full SOAs!

Tim

[pardo-bsso]

I have done it before where TVS diodes provide the clamping, and with much higher energy capability than any MOSFET of equivalent size.  The result is an impressive envelope in limiting mode / fault conditions.  (I designed for a 30V 20A load range, with 150ms fault duration.  A MOSFET of the same size, in linear mode (no 2nd breakdown), will hardly last 10ms doing that!)

Tim

Apologies in advance for hijacking your thread, but I'm curious about this. Can you share a bit more about that design?

[T3sl4co1l]

Sure.  This is the basic architecture:



D1/D2 return to a common ground of course, but this is optional when TVS are used.  The symmetrical design allows bidirectional current flow (V1 and V2 must both be positive, but neither needs to be greater than the other).

Waveforms (DCM):



I developed this into a discrete control circuit (hysteretic control, plus a timer and flip-flop for run/time-out/stop),



the controls run for a few months on a 9V battery; I don't think an IC-based solution can perform better, given what ICs are available at the moment, but a purpose-made IC would vastly outperform this.

I don't have complete schematics released anywhere though.

Tim

[johansen]

it's not clear which generation you're referring to...

I'm not sure how anything can survive on more than sheer luck with "half the chip blown off"?

I might have the part number later today.
Edit:
was mistaken earlier. the fet that failed was shorted on but with similar on resistance as standard

so anyhow.. i told my friend this idea of yours to bypass the SOA limitations by dumping the energy into avalanche, and his comments were that "you need to get the actual SOA curve from the manufacturer directly. the nice straight lines in the datasheet are for dummies."

he doesn't seem to think it will work because the problem is heat causes a positive feedback loop, and seems to agree with me that it could work if the avalanche voltage increases with heat, not decreases. which is unlikely.

[David Hess]

As for SOA, older types didn't have enough power density to run into 2nd breakdown, more or less; and lateral types either don't, or are prone to stability regardless (for reasons not easily explained by Vgs(th) tempco alone; though the tempco inversion point I think does fall quite low with some of these?).  Trench types are dense enough to risk 2nd breakdown, and SJ trench even moreso; it's a miracle that many don't!  In short, read the datasheet: no general conclusion applies these days.  Even some IGBTs (having even higher power density than SJ MOSFETs!) boast full SOAs!

The lower power density of old lateral types also yielded lower junction-to-case thermal resistance so higher power ratings for a given current and voltage rating.  Where it gets more interesting is that they also had lower gate charge requirements than modern parts.  This was a problem when replacing the power MOSFET in the off-line switching power supplies of Tektronix 22xx series oscilloscopes; "modern" vertical power MOSFETs had to be severely derated compared to what was originally used.

Unfortunately there are no modern replacements for these parts with both low gate charge and high power ratings.  Manufacturers talk about "low gate charge", but that is in comparison with earlier vertical power MOSFETs.