My Linear Regulator Circuit is Unstable

[nictinkers]

I was asked to design a power supply for a client. After some back and forth, the specification was agreed as 50 VDC ±10% at 5 A, with other versions (like 24V/20A) to come by modifying parts later. The regulator had to follow a traditional linear layout (transformer, full bridge, linear pass transistors).

So I came up with the circuit below. It was stable in simulation, (LT Spice file attached) but I'm a suspicious fellow and put footprints in for a bunch of compensation components. I breadboarded it up and, while a bit noisier than I'd like and requiring a judicious capacitor here and there, the circuit worked.

So I worked up some PCBs and put it all together. Unloaded they give me 50VDC out but as soon as there's a little load the circuit goes unstable. There's noise (peaking around 80 MHz) all through the circuit.

I understand that P-channel regulators are an unstable configuration (though the level shifting I'm doing here wrinkles things a little) and that instability is caused when the system is amplifying signals that have sufficient phase shift as to create a positive feedback effect. I think I can return the regulator to stability by reducing the gain in the right place or by somehow adjusting the phase of high frequency components on the loop, but I'm lost as to how to do this.

[free_electron]

wow...
where to start ...

driverstage :
Q2 ... put some load from base to ground, actually get rid of R15 and get rid of d13 ( why do you put that there in the first place ? )

amplifier stage : get rid of c11. you are slowing down the reaction time of the feedback you are making an r/c
C13 : slap in a few 100 pf to stop high frequency oscillations.

and what's with all the whacky resistor values ? i can't think straight with values like that.

you want 0 to 50 volt rigt ? with 0 to 10 volts input ?
that is a  gain of 5, you got  a gain of 10 ...

what is that 0..10 volt in 500mV to -500mV ?
that whole block with the vref and u4b doesn't make sense to me.

Now, r19 r18 r17 r16 need to be much smaller. the mosfets react way too slow
your loop is very unstable. First of all the opamp can't see immediate changes in the output due to C11 ... it reacts with a delay. This causes overshoot. which it has to compensate ... causing oscillation .. then when it tries to turn off the fets the gates are discharged too slow due to the high value resistors.

i would get rid of those resistors and put a current source there.
that would make a 'hard' driver for the mosfets.

the schematic below makes a simple current source. the current is set by the Rx and the three 1n4148 diodes. 1 diode is used to drop the base-emitter voltage and the other two make 1.2 volts.
So , if the voltage across Rx is 1.2 volts then the transistor will turn itself off. to get 1.2 volts there we need 60mA to be running. ( 20 ohm )

That 60mA is deviated to ground using Q2. whenever the opamp reacts and controls Q2 the current will either inject in the gate capacitors turning the mosfets off , or the gates will get discharged through q2.

you may need a small resistor ( 20 ohms) between the collector of Q2 and the gates of the mosfet. Not for the current ( the current cant be more than 60mA set by the current source, but to protect the 15 volts zener when Q2 pulls really hard ...

That zener needs to be 3 watt ..
Q1 and Q2 need a heatsink as the dissipate up to 3 watts.
make sure those transistors can hold 100 volt and run 100mA collecotr current and dissipate 3 watt.
To126 may not handle that. i would look at TIP31C and its complement

[madshaman]

@free_electron: you're a generous individual, :bow:

[nictinkers]

Thank you, free_electron, for taking the time to reply, and doing so in such detail. It's greatly appreciated.

R15 was an attempt to find stable operation by limiting the gain - the emitter-follower would limit the current pulling charge from the base to about 12 mA.

D13 exists to prevent damage to Q2 when the output of the op-amp is negative. While I wouldn't expect this in normal operation, it's there just in case. Looking at it, the negative voltage rail isn't actually used anywhere here, so I might replace that rail with GND and remove the diode. There are limits to how much I want to hack away at the PCB, though.

R9 was 1k to allow the inhibit logic to shut the regulator down without causing the op-amp to have to supply its short-circuit current.

I apologise for not giving more description of the circuit. The supply is meant to be 50V ±10%. U4B takes a control signal from a manual control or a remote control unit and adjusts the reference voltage ±10%. If the control signal isn't present (no remote control unit installed, broken wire or other failure conditions), the amplifier passes the 5V directly through.

I'm not sure which resistors are the wackiest, but R3 and R4 divide the reference voltage. The intention was that R3 was always loaded, and R4 only loaded in cases where the output is to be 24V instead of 50V.

Thank you for suggesting a current source - I'll look into ways of implementing it that don't involve re-spinning the PCB. I might be able to get away with a daughterboard. The changes to C11 and C13 are pretty obvious now that you've mentioned them.

[nctnico]

IMHO removing C11 and D13 will improve things a lot. Playing a bit with the value of R9 may also help to change the response.

[dannyf]

requiring a judicious capacitor here and there

Once you are there, the design is toast.

[IanJ]

Hi,

If you really want to try and keep your existing board then I've had some luck using an LM8272 op-amp in a similar situation of driving mosfets directly........high current output drive (+/-65mA) and specifically able to drive high capacitive loads (TFT's etc)..........So you might get lucky. However, free_electron's design is the best long term bet.

http://www.ti.com/general/docs/lit/getliterature.tsp?genericPartNumber=lm8272&fileType=pdf

Ian.

[free_electron]

Changing the opamp doesn't do much as the opamp doesn't see the capacitve load of the mosfets , it sees the base of the bipolar transistor.

If you don't want to fidget with the board :
Get rid of the capacitor in the feedback network like i wrote , and add the dampening capacitor across the opamp. You can also add 1 meg in parallel with that dampening capacitor.

[gotvolts]

Have you tried measuring the loop response?  (assuming you have the proper test equipment and you find a suitable injection point)

Or at  least try measuring it in your simulation program?

If you can do both, you can try seeing if they match and then tweak your simulation model to get the real world characteristics of the loop.

[nictinkers]

I'm fairly sure I don't have C11 installed on the breadboard or the PCB - it was on the circuit for the footprint in case I needed to load something there. I may have accidentally loaded it thinking it was a bypass cap when I was putting the boards together. I'll have a look today.

My gut feeling was that I wanted to reduce the gain to make things more stable, but the advice here seems to be to be strengthening the drive to the transistors. Doesn't that (generally speaking) result in a smaller gain margin?

Similarly, if I have noise on a signal, my first thought is to filter it out with a capacitor. Here in the control loop, C11 and R5 would form a low-pass filter to reduce high frequency components of the noise. I feel that I'm missing some conceptual leap. C11, if present, would slow down the response, causing a phase shift that results in instability. How do you judge the merit of these two competing actions (cap rolls off high frequency vs cap causes phase shift) to know whether putting a cap there is worth it?

I should have sufficient equipment available to measure the loop response (I've got frequency generators, a 100MHz scope and a DSA815-TG spectrum analyser I can use), but I'm not quite sure how I'd do so. Do I replace the reference input with a function generator and sweep the frequency, measuring how much of that frequency appears at the output? Or do I stick the frequency generator in the feedback path?

Is it sufficient to capacitively couple the generator in? I'm using my isolation transformer to power the rig at the moment (the industry it's going into uses 110VAC so I needed to step down) but I can rig up batteries and an inverter to give another isolated power source.

[free_electron]

but the advice here seems to be to be strengthening the drive to the transistors.

the strenghtening of the drive does not add gain !
what i proposed is a current mode driver.

Forget the spice simulation and all the mathematics crap , let's reason this through logically for a second and see what happens.

Let's first take a look at the used pass element : the mosfets.
Here is the problem with mosfets : the control ciruit perceives the gate of the mosfet as a capacitor.
So , to control the mosfet you either need to send charge into the gate or pull it out.
Charging in your system is fast. if that MJE transistor goes into full conduction you are CHARGING the capacitor quickly. ( the Source of the mosfet is at 50 volts, the gate is being pulled towards ground so you are CHARGING the gate capacitor )
So the mosfet will go into conduction very quickly.
The effect is the mosfet goes into conduction very quickly so the output voltage goes up.

Now, the change in the output voltage is fed back to the opamp using the 18k and 2k resistor.
but the 2k resistor has a capacitor across it.
The opamp senses that point in order to compare it with the setpoint (what you want)
Since you have a capacitor there , the actual change in the output is slowed down ( that capacitor has to charge or discarge )

So the 'error signal' ( the feedback behaves as an error signal. The opamp has 2 signals to deal with : What you want and what iti really is. Teh delta between them is the error ) is delayed because of the capacitor across the 2k resistor.

So, by now the mosfets are in conduction (this happened fast as you can charge the gates fast) , output is rising and it will take time for the opamp to register this due to the delay caused by the charging of the capacitor across the 2K resistor.

So finally the opamp is catching on and decides 'whoa, we're getting waaay to much voltage here at the output. and slams on the brakes. the opamp will start turning off the MJE transistor. Now , for the mosfets to stop conductiong the gate needs to discharge ... how ? the only pathway is formed by the 10k resistors between gate and source... so this takes time.
the mosfet can turn on fast because the MJE basically can pull the gates to ground and put 50 volts into it ( ok limited by the zener to 15 , but there is virtually no current limit apart from your 1 kiloohm )

So it takes a while for the output voltage to 'sink back down'. Worse, the feedback incurs an additional delay due to the capacitor across the 2K
so the opamp sees an error signal that is penalised by 2 delays : the slow turning off of the mosfets, and the slow registration of the real output voltage due to the cap across the 2K resistor.

so the opamp sits there really hard turning off the MJE but nothing happens !
 your output voltage now goes below your setpoint, the mosfets are not conducting but the capacitor across the 2K is still discharging... so now your output is below 50 volts.
Now we get to the point where the setpoint is equal to the voltage across the 2K. the opamp is happy.. but, in reality the output is too low , the opamp just doesn't know it yet. the capacitor keeps discharging and the opamp reacts turning on the mosfets...
since it takes a while for the voltage across the 2k to rise again there is a moment where the opamp goes 'the output is too low, i turned on the mosfets but nothing is happening , i'll open em up a bit more....

so the delay incurred by the charging and discharging of the capacitor across the 2k resistor basically creates a delayed error signal. No matter what the opamp tries, the feedback is coming in too slow and it can't regulate well.
It is perpetually caught in a state of 'overshoot' and 'undershoot'.
So it essentially oscillates !
and that is what you are seeing.

The feedback should be instantaneous. so : no capacitor across the 2K !

now, there is still the proble of the mosfets turning off slowly...
that is where my current source helps.
(it i actually a current sink towards 50 vots rail... this is going to sound confusing ... bear with me )

So , here is how this trick works. : The current source supplies ALWAYS 60 milliampere (with my given values)
To turn the mosfets on the MJE transistor draws the 60 milliampere to ground and draws the gate charging current as well ( the gate charging current from the pmosses comes from 50 volts , into the source, across the gate capacitor , out of the gate and  into the MJE transistor ) So to turn on the transistors we are drawing current OUT of the gate. this current charges the gate.

To turn off the mosfets i turn off the MJE. the current source still wants to provide 60milliampere but it cant go through the MJE to ground. so it goes into the gate of the mosfets , DISCHARGING the gate voltage.

it sounds cnfusing. let's look at the voltage signs.
the Source of the mos is at +50 volts. to turn on i brange the gate LOWER than 50 volts, at 35 volt ( limited by the zener diode , you don't want to fry the gate oxide in the mos )

so the gate is NEGATIVE in respect to the 50 volts.

the current source now pumps current into the gate bringing the gate MORE POSITIVE so the gate goes back towards the 50 volt. it does this very quickly as we are feedin it 60milliampere.
assume the gate was charged with 15 volt ( 50 volts on source, 35 volts on gate ). to discharge across 10k you divide 15 volts by 10k and you end up with a discharge current of 1.5 milliampere...
As the gate voltage goes down , at 5 volts ( 50 volts source, 45 volts gate ) you still have the 10k... now only 0.5 milliampere is flowing.. it discharges slower !.
but at 5 volts gate voltage that mos is still conducting ! so your output voltage is still completely out of whack

The current source solves this R-C discharge curve. no matter what the gate voltage , it will send 60 milliampere in that gate !
Once the gate has reached 1.2 volts the current source becomes non functioning ( the transistor cant conduct anymore ) but that is ok. with 1.2 volts teh mosfet is off ! (50 volt on source, 48.8 volt on gate ) mosfets need about 3 volt before they start doing anything ...

You can throw all that stuff into equations and simulate the snot out of it. People like to throw out numbers with fancy names like 'phase margin' or 'loop response'
The phase marging is bad , or the loop response is bad.

OK smartass, i can tell you that already : the damn thing is oscillating ! you just proved it was oscillating.. but i knew that already... tell me how to fix it now
and answering you need more phase marging is NOT an answer. tell me what component to add,remove or change value... blank stare...
they know what number is off , but they can't thell you WHAT makes it be wrong

Simulators and mathematics are not a substitute for understanding how a system works. (before this ends up in another meth flamewar , yes you need the mathematics to work out the numbers. but if you dont know what the numbers are for ... they are useless )

There is one thing you need to remember , and this is a universal truth : the circuit doesn't lie ! An assembled electronic circuit will under any circumstances do what it does. That may not be what you want it to do or think it should do. But you are irrelevant ! the circuit does what the circuit does. yelling at the components and showing them a bunch of diagrams and equatons doesn't help. Electrons are illiterate, stupid, boneheaded and flow into the path of least resistance (pun intended). you can't blame them nor hold them accountable. Their attitude towards mathematics and simulations, and anything else for that matter, is 'f-you'. I see a charge there , which is opposite of mine, i'm going there !

[free_electron]

http://www.educreations.com/lesson/view/current-source-control-of-a-pass-element/13528394/?s=zuMRtM&ref=app

There you go 

[madshaman]

I'd add that if one understands what the circuit is doing, and *measured* the phase response of the control loop (or derived it from the frequency response), you'd also see why it oscillates as the phase delay is turning the negative feedback into positive feedback; so you must either filter out those frequencies which are delayed and/or increase the bandwidth of the control loop (in which case you still need to do filtering but at a higher cutoff).

That's pretty much exactly what free_electron's post is describing to you in more straightforward terms.

I hate "magical" terms and formulas too.  There's nothing wrong with math, but you need to understand *why* the math is the way it is, *why* the math is helpful, *where* to apply it, and you need to apply the math to *measured* values of the actual system, not just simulations or analysis of ideal models.

[madshaman]

P.S.  You also need to know *why* the measured response of the system is what it is, and math will help you there too.  Again free_electron's post is precisely indicating that.

(And also from a point of view of much more experience and knowledge than myself)

[nictinkers]

Thanks Vincent! Thank you again for taking the time to reply and for your video.

I double-checked and none of the boards have C11 loaded.

Interestingly, the circuits here: http://tangentsoft.net/elec/opamp-linreg.html have a large capacitor where I have C8 in the schematic posted. This is described as being to "[roll] off the gain of the regulator ... so that high frequency noise isn’t amplified by the error amp."

I agree that the current source will turn the FETs off faster, and that the voltage at the gate will ramp linearly instead of exponentially, but I'm not sure that this is so fundamentally different. There will still be a delay involved, and so still the potential for oscillation.

The total FET input capacitance is 20nF. Discharging the gate voltage from 3V to 1.2V with the four 10k resistors takes about 50µs. (V(t) = V0*e^(-t/RC)) Charging it through my 1k emitter resistor takes about 3µs. (CV=It) I can see that those are unbalanced. If I use smaller pull-up resistors and/or a larger emitter resistor I could make the action more symetrical.

With your current source configuration, charging the gate is limited by how much current Q2 can sink. This is based on the gain of Q2 and the current that can be supplied by the op-amp. Assuming the op-amp can supply 20 mA and Q2 has a gain of about 25 (TIP31C), you've got around 440mA/81ns to charge, and the 60mA/600ns to discharge. (CV=It) This is faster by a factor of about 50 to 100 (though still asymmetrical.)

But this is a DC power supply and I don't care too much about high frequency transient response. Couldn't I just get away with a lager compensation capacitor?

My forget-the-maths-crap understanding of the compensation cap is that it sends some fraction of any change at the output back to the negative input via a fast path. It's the as-fast-as-possible response, and it's presence fools the op-amp into thinking the system output is where it should be for a little while. The length of the little while needs to be enough for the actual control action of the FETs to get the output voltage to where it should be. A large capacitance would allow for a longer hold-over time.

I am trying your current source circuit on the board. The current source (based on a TIP32C) provides ~80mA well enough but I seem to pop the TIP31C at Q2 as soon as I apply power. This fails over to fry the base resistor and/or the op-amp. There may be something stupid I'm missing, though, so I'm going through and rechecking everything.

I also have a small suspicion that my problem might not be the main control amplifier, but the 0.22? resistors on the source of each FET. They're there to ensure the FETs share the current somewhat evenly. They are a simple negative feedback system, but being large wire-wound resistors, maybe there's some inductance that is causing overshoot and oscillation.

[AJBotha]

wow... free_elektron explains stuff... LIKE A BOSS!!

[qno]

Personally I would go for output transistors.

Mosfets are difficult to control when used in the linear mode.
A mosfet has a knee in its linear range.
This means very little gate voltage change has a large influence on the drain source current.
It is also depending on where in the gate voltage knee you are.
This makes tuning the control loop difficult.

Mosfets are good for switching fully on to fully off.

On the other hand a transistor has a a resonably flat IB IC diagram.

[nictinkers]

I know what you're saying qno, but P channel FETs do have some advantages. It's much easier to get high power rated P-FETs than PNP BJTs. FETs need less voltage across them in operation, which allows the bus voltage to be a little lower, leading to less power dissipation.

I had mistakenly thought another advantage of FETs is that they have a positive resistance temperature coefficient - you can stick them in parallel and if one takes more current than the others it gets hotter and its resistance goes up, lowering the current. I ordered a bunch of FETs on that assumption.

It turns out that only holds when FETs are turned on hard (as is the case in switching topologies), not in the linear region. That's why I've got small value resistors on the source of each FET, as it forces load sharing across the devices.

[free_electron]

Putt hose 0r22 in the drain instead of in the source.
It's worth a try...

[miceuz]

A mosfet has a knee in its linear range.

When I was designing my own power supply I went for mosfets, but have spent reasonable time to look for ones with more flat response. I guess that was just beginners luck, but I had no oscillation problems in constant voltage mode.

[megajocke]

If you see 80 MHz oscillation the source is probably local oscillation in the output stage itself. Try adding ferrite beads or resistors of about 100 ohm or so in series with the gates. MOSFETs can easily form a Colpitts oscillator topology because of the inductance in the wiring and the device capacitances.

But that's not likely to be enough. There are lower frequency problems too in the circuit as has been pointed out. Somewhat simplified you need to ensure the feedback loop gain crosses unity with an adequate phase margin which requires that the slope can not be much higher than 20 dB/decade (6 dB/octave).

With your current topology the opamp contributes one LF pole, the capacitor in the feedback path a second and the MOSFETs a third because they are driven from a high impedance. Each introduces a phase lag of 90 degrees around what would be a suitable crossover frequency.

There is also a fourth pole caused by the output capacitor but it is cancelled by the ESR zero - at least if you make sure to cross over above the ESR zero. So you will have a crossover with a slope of about 60 dB/decade with your current circuit (if crossover happens sufficiently above the ESR zero) and it will be unstable.

A circuit like this can be made stable by keeping the high impedance drive to the MOSETs (either with resistors or a current source) and giving the error amplifier a shelving lowpass type response. That implies a series RC feedback configuration for the operational amplifier working against the feedback resistor.

The resistor in series with the emitter of the transistor between the opamp and MOSFETs is useful to stabilize the transconductance of the stage over varying operating conditions but also limits the current through this transistor if the loop goes out of regulation, for example caused by low input voltage.

[megajocke]

Here's the kind of circuit I mean. Referring to my attached diagram:

The gate resistors (R3 and R7) suppress local oscillation in the output stage MOSFETs. Without them the inductance of just a few centimetres/inches of wire is enough to make the output stage oscillate.

The R8 biasing resistor and D1 zener are connected outbound of the current sense resistors. The resistor doesn't matter much (but then you can share one for all mosfets) but having the zener outbound makes for a somewhat well defined gross current limit together with the source resistors. Having zeners right at the mosfet gates too won't hurt of course.

Making R8 low can be beneficial because it reduces the time constant of the output stage. If you choose R8 = R4, then at DC you will have a gain of -1 from the opamp output.

Rcomp and Ccomp should be tweaked for the number and type of MOSFETs used. If R8 is chosen low they may not be required because the loop crossover will fall below the output stage pole frequency even without them.

As for chosing their values otherwise, keeping the Rcomp*Ccomp time constant equal to the MOSFET output stage time constant is a possibility which cancels the pole of the output stage. With such a constraint, the other free parameter can be chosen to get the desired crossover frequency. A large Rcomp (together with a low Ccomp) makes the regulator load response faster.

A current source at the R8 position can improve DC performance such as ripple rejection but makes the output stage pole frequency zero and will definetely require this RC-type compensator.

[Kevin.D]

quote :- "So I worked up some PCBs and put it all together. Unloaded they give me 50VDC out but as soon as there's a little load the circuit goes unstable. There's noise (peaking around 80 MHz) all through the circuit"

Like what Megajocke said ,if your oscillation is that high in frequency it's  to fast to be your control loop ,it's probably local fet oscillation , one cause can be mutual excitation from parallel mosfet's and it's usually at the kinda frequences your observing. Megajockes already told you  how to prevent it but heres a interesting pdf on it you can read http://www.google.co.uk/url?sa=t&rct=j&q=&esrc=s&frm=1&source=web&cd=3&cad=rja&ved=0CDcQFjAC&url=http%3A%2F%2Fwww.microsemi.com%2Fdocument-portal%2Fdoc_download%2F14693-eliminating-parasitic-oscillation-between-parallel-mosfets&ei=yPyHUpTpJIO0hAf9lIHICw&usg=AFQjCNFx4nIFZLZHdXErKAATadkeupfzdg&bvm=bv.56643336,d.Yms

[megajocke]

That was an interesting article. Thanks!

By adding some (unbalanced) lead inductances to the simulation I did see that effect the article shows.

Even though the source impedance driving the parallelled MOSFETs is high, which might seem safe at a first glance, the parallell connection can interact and oscillate at 10s of MHz.

[madshaman]

Learning a lot of practical stuff from this thread :-D