My Linear Regulator Circuit is Unstable

[nictinkers]

Thank you megajocke and Kevin for your replies, you've been really helpful. Sorry I haven't gotten back here sooner.

Ferrite beads were the key to the high frequency oscillation. The high frequency kicked in when I had four FET stages loaded but was absent with fewer in many configurations, so I'm sure Kevin's article is right on the money.

The RC op-amp feedback is definitely more effective than the cap alone, but I found I had to go a bit higher than 1nF.

I've got two of us working on this, converging from different directions. The other engineer has something that is stable but so far has only been using two output FETs. He's got (smaller) resistors instead of the current source and hasn't change the pull-down transistor configuration:



I don't really want to ship with only two output FETs. While the power dissipation would be okay, I'd prefer to spread it across four devices as the heatsinks will be more effective. I'd also like to understand and solve the problem so that when it comes to do the 20A version we don't have to go around again.

I'm working through with more of the suggestions in this thread. I've removed the diode following the op-amp and am running the op-amp from just the +12V supply. I've kept the resistor between the op-amp and transistor because it prevents the op-amp from going into current limit in unregulated conditions and helps prevent cascading component failures if, for example, Q2 fails and the bus voltage appears at its base.

I've reduced the drive current to about 25mA. This was because the experience with the mico-U heatshinks I could fit tells me they're good for about 2W power dissipation. I've kept the emitter resistor on Q2 but made it smaller so the current the charge the FETs is the same as to discharge.



Unfortunately this is still unstable. Under load, I get 10kHz oscillation. The frequency stays the same but the amplitude grows a little with load.



I think I'm getting close, and just need to combine the two configurations, and I'd like to experiment more with the values of the Rcomp and Ccomp.

My main remaining question is: how would I hook a generator and scope up to see the phase and gain results? Do I perturb the reference or the feedback path? Or something else? Is there a way of using a spectrum analyser with tracking gen to sweep through and give me some more insight? (Unfortunately I don't have access to a vector analyser, so I appreciate I could only see the gain that way)

[PChi]

I think that you could perturb the reference or I vote for feeding a signal generator output via an AC coupled resistor into U4A inverting input. I have produced a Bode plot for a power supply and it proved difficult to see the perturbing signal in the noise and ripple but it was a long time ago and it was a switch mode power supply.
I guess that the ultimate is to use somthing like a frequency response analyzer like that available from http://venable.biz/ but I have no personal experience them. Probably out of the question due to cost.

[blackdog]

Hi nictinkers 


Try this...
Choose for the tip41 a faster transistor, BD139, D44H11 enz Ft >15Mhz.

Give each a FET gate resistance of about 15 to 47 ohms, direct on the gate!!!!

Make C8 10nF, Delete C9

Sometimes you need a small resistor directly connected to the current source transistor Q7.

C13 is to big, start with 330pF!

Remove D16

My 2 cents...

Kind regarts,
Blackdog

[megajocke]

You really need to get the circuit stable before you can measure the stability margins.

I'd suggest not using the current source but to use a resistor instead. If you use a current source your feedback loop has three low frequency poles (opamp with compensation, mosfet gate circuit and output capacitor with load) contributing up to 270 degree phase lag at low frequencies.

This is cancelled by two zeroes (output capacitor ESR zero and opamp compensator zero), bringing back up to 90 degrees of phase margin, but it means your crossover frequency always have to lie sufficiently above these zeroes and below the frequency at which other effects such as driver BJT and opamp bandwith start to contribute phase lag to have good phase margin.

When the load varies, the transconductance of the FETs will vary. At low load, the transconductance will be low and the crossover frequency likewise, tending to fall into the low frequency region where the phase lag is large. And when the load current is high, the crossover frequency will be high, tending to go into the region where the opamp and transistor worsens the phase margin. Also, if the circuit starts to oscillate its effective gain lowers tending to bring the crossover to the unstable low frequency region.

But if you use a resistor instead of the current source you can never have more than 180 degrees of phase lag at low frequencies and your circuit will be much easier to stabilize. Even if the crossover frequency drops it will never go below 0 and start to oscillate.

Your component values are probably close to OK. I'd suggest around 1k instead of the current source. You don't really need much drive current for the FETs in an application like this.

If you manage to get it stable, a good next step is to see what the response to a step change in load current is and tweak component values if it is not good enough.

[GK]

The I-source is definitely desirable for ripple suppression. I'd just apply local feedback to the common emitter stage to define its collector impedance and push the pole formed in conjunction with the MOSFET input capacitance up and out of the way. You could even use a "beta-enhanced VAS" and Miller compensation with a zero, and have the error amplifier quasi-integrator take over after that.

EDIT: oops, didn't look at the circuit close enough and just assumed it was a source follower for the series pass. I wouldn't bother with an I source in that case either. Though why would you want a common-source series pass with its intrinsically high output impedance for a PSU anyway? That's a significant performance compromise that is usually only made when low drop out is required. Not the case with the design here.
 


 

[dannyf]

Unfortunately this is still unstable.

With all the high speed devices, active loads, and gazillion capacitors, it would have been a miracle for the design to be stable.

I would suggest that you do more home work, simplify the design, start with a bare minimalist framework, slow down the mosfets (add some gate stoppers, etc.), and use old fashioned resistors. You may have a chance that way.

You have to understand that a high-speed power amplifier (aka a psu) is very difficult to stablize. You have to make compromises between speed and stability / regulation.

[nictinkers]

Okay, this is what looks like it's going out the door:



The key changes were:

• Ferrite beads on the gates of the FETs to stop the high frequency oscillation
• The RC feedback network on the main control op-amp suggested by megajocke
• Removing C5, which is mind-bogglingly obvious once you see it. It was making the reference voltage oscillate

We've also increased the strength of the FET drive by reducing the pull-up resistors and the emitter resistor of Q2. The source resistors were bumped up a bit to better share the current through the FETs.

@blackdog: thank you for the suggestions, please don't think I missed them, I've just been focused on the design. The transistors you mention are only rated to 80V and the bus voltage can head north of 90V when the supply is unloaded and the line voltage is high. I'd welcome suggestions for a fast transistor with a 100V VCE rating to try in future designs.

I did try a small capacitance at C8 - something around 680pF did reduce the noise a little (maybe 10%) but 10nF caused more problems than it solved.