Author Topic: My PSU design ripple and noise with picture measurements  (Read 41012 times)

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My PSU design ripple and noise with picture measurements
« on: August 22, 2021, 06:55:55 pm »
Hello

I designed a PSU as a replacement PSU for Dreamcast using TPS62913 which promises total final noise and ripple of 1 mV p-p but I got around 80-100mV p-p despite following the datasheet and design layout recommendation. Other third-party PSU delivered near identical results despite having inferior parts and basic design. I added LC filters and ferrites plus bulk filtering caps 1000uF with 22uF ceramics for the input 12v rail but still I got this result.

Input 12v is supposed to come from cheap 12v PSUs, mine has 250mV p-p ripple and noise as shown in below pictures...

so:

1- does this mean that even good buck regulator design just cannot eliminate input ripple\noise? I mean it will get reduced but still will pass through?

2- what solution to achieve such low figure of 1mV or near it?

3- is adding huge inductor Pi filter will solve it? I only had 4.7uH for 12v filtering plus 1000UF elec cap and many ceramics.


pictures are labelled so you can recognize it.

for your kind help.

regards,

Offline ezalys

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Re: My PSU design ripple and noise with picture measurements
« Reply #1 on: August 22, 2021, 07:04:27 pm »
we’d need to see your schematic and layout. Also what’s the signal on the scope look like if you do the exact same measurement but with the power supply turned off?
 

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Re: My PSU design ripple and noise with picture measurements
« Reply #2 on: August 22, 2021, 07:08:39 pm »
additionally, I think it’s bad engineering to just throw LC filters at the thing. I’d like to know what the cutoffs are of the filters, the parasitics of them, the layout, all these things will contribute. It’s also true that no regulator will eliminate all noise, they just suppress it with a particular amount of suppression per frequency. LC filters, bulk caps, ferrites, and regulators themselves are tools in your toolbox to be applied deliberately to reduce noise.
 

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Re: My PSU design ripple and noise with picture measurements
« Reply #3 on: August 22, 2021, 07:14:08 pm »
Who promised 1mV p-p ripple out of a buck converter? Oh TI did TPS6291x 3-V to 17-V, 2-A/3-A Low Noise and Low Ripple Buck Converter with Integrated Ferrite Bead Filter Compensation using 8A ferrite bead BLE18PS080SN1.
I think your expectations are high and a Dreamcast doesn't require such low ripple.

Your PCB layout, scope grounding, choice of capacitors, ferrite bead- are all critical. You've got a 50mV noise floor so you cannot measure below that anyhow.
 

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Re: My PSU design ripple and noise with picture measurements
« Reply #4 on: August 23, 2021, 09:06:33 am »
additionally, I think it’s bad engineering to just throw LC filters at the thing. I’d like to know what the cutoffs are of the filters, the parasitics of them, the layout, all these things will contribute. It’s also true that no regulator will eliminate all noise, they just suppress it with a particular amount of suppression per frequency. LC filters, bulk caps, ferrites, and regulators themselves are tools in your toolbox to be applied deliberately to reduce noise.

I didn't do calculations for LC filters but rather kept it straightforward and simple. I knew 12v will be very noisy, so I put them. I will put schematic once I return from work, even though it is not open source and should be commercial product... but it is ok.

Quote
Who promised 1mV p-p ripple out of a buck converter? Oh TI did TPS6291x 3-V to 17-V, 2-A/3-A Low Noise and Low Ripple Buck Converter with Integrated Ferrite Bead Filter Compensation using 8A ferrite bead BLE18PS080SN1.

Yes, this is the IC. I have used different passives (from LCSC) than those of TI, but I think the ferrite is the same. why the results differ so much?

Quote
I think your expectations are high and a Dreamcast doesn't require such low ripple.

I kinda went with their data and demonstration, or else what extra benefit to get from this IC over a regular one?

Dreamcast is an old console which uses analog video signals which are sensitive to noise. analog video is 1v only, so 100mV ripple and noise will have an effect. Generally, less noise and ripple the better. Making a cheap PSU which has low noise\ripple is good too.


Quote
Your PCB layout, scope grounding, choice of capacitors, ferrite bead- are all critical. You've got a 50mV noise floor so you cannot measure below that anyhow.

Scope is not mine, it is in a fablab which is far away from me. Not accessible easily due to far distance and so on. It is gw instek gds-1152a-u 150 MHz 2 channels. I used normal probe with putting the probe ground to psu ground and then get the signal. I wonder why I got such a huge noise floor.

If I got 60-90mV noise for it, does that mean its real noise\ripple is just 10-40 mV p-p since the extra 50mV is just noise floor?


what solutions do you suggest to achieve this low values or near them?

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Re: My PSU design ripple and noise with picture measurements
« Reply #5 on: August 23, 2021, 07:26:56 pm »
Here is the schematic and layout.

Offline T3sl4co1l

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Re: My PSU design ripple and noise with picture measurements
« Reply #6 on: August 23, 2021, 08:02:56 pm »
Why isn't ground poured under everything?  Most especially the regulators themselves, but also contiguously under the board?  Likely the ripple measurement is largely common mode (due to the high ground impedance between connectors)..?

C6-C8, C10 and C12 do absolutely nothing; I don't know where such tiny values came from.  The ferrite beads largely do nothing as well, they saturate under bias (typically >50mA, depends on value and size -- they may still be seen to help out at light loads).

Bleeder/load resistors should not be necessary.  If you are finding instability, check component values, or select a regulator with external compensation so it can be better tuned.

Note that such large ceramics (22uF, in, what are these, 0805s?) run out of capacitance quickly under DC bias, not so much at 3.3V, a bit at 5V, definitely at 12V.  This is probably still fine because of the parallel quantities, but keep this in mind when going from design calculations to component selection.

Since you're using electrolytics (well, polarized something anyway, maybe they're polymer I don't know), I don't get the large quantities of 22uF chips; a couple electrolytics would do as good a job, plus one or two ceramics to "take the edge off".  Otherwise, if you're not squeamish about the cost of so many caps, why not just go all in, who needs electrolytic?  (Except maybe at the input, if there's a need for bulk capacitance say for mains filtering or hold-up time.)

The 3.3 and 5V outputs seem reasonably well filtered near the connector, but V12 is not at all.  But the input is heavily filtered (but only differential mode).

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Offline GigaJoe

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Re: My PSU design ripple and noise with picture measurements
« Reply #7 on: August 23, 2021, 10:00:51 pm »
chip operated at 1-2Mhz,  radio frequency , extremely short connections,  filled ground, dual side for ground, shielding, etc
pdf define a spec even for caps, due to freq. and resistance.

proper scope measurement, your scope tail catch everything , something like that
https://www.cui.com/blog/how-to-measure-ripple-and-transient-in-power-supplies

huge caps or L doesn't help much due to freq.  find caps - freq. dependence graph.


 

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Re: My PSU design ripple and noise with picture measurements
« Reply #8 on: August 24, 2021, 09:36:28 am »
Quote
Why isn't ground poured under everything?  Most especially the regulators themselves, but also contiguously under the board?  Likely the ripple measurement is largely common mode (due to the high ground impedance between connectors)..?

I followed datasheet layout recommendation for ground pour. I also thought it would be a good idea to make noisy 12v ground far from clean regulated output ground due to what many people are assuming about separating ground for return current path and not mixing bad noisy signals with clean ones. On a side note, I am changing my idea towards making one unified ground pour for everything these days as some credible people are saying this nowadays.

Quote
C6-C8, C10 and C12 do absolutely nothing; I don't know where such tiny values came from.  The ferrite beads largely do nothing as well, they saturate under bias (typically >50mA, depends on value and size -- they may still be seen to help out at light loads).

I added them as an extra caps to deal with high frequency stuff. I also put Pi filters as you see but they don't seem to have done much. I didn't do any calculations though.

Quote
Bleeder/load resistors should not be necessary.  If you are finding instability, check component values, or select a regulator with external compensation so it can be better tuned.

Adding minimal load like this is always best and doesn't cost a thing. no harm too.

Quote
Note that such large ceramics (22uF, in, what are these, 0805s?) run out of capacitance quickly under DC bias, not so much at 3.3V, a bit at 5V, definitely at 12V.  This is probably still fine because of the parallel quantities, but keep this in mind when going from design calculations to component selection.

0805 is the largest I can tolerate since it is 50x50mm board. Putting many in parallel is also helpful as you said.

Quote
Since you're using electrolytics (well, polarized something anyway, maybe they're polymer I don't know), I don't get the large quantities of 22uF chips; a couple electrolytics would do as good a job, plus one or two ceramics to "take the edge off".  Otherwise, if you're not squeamish about the cost of so many caps, why not just go all in, who needs electrolytic?  (Except maybe at the input, if there's a need for bulk capacitance say for mains filtering or hold-up time.)

regulator IC doesn't require elec. caps and actually does not require a lot of capacitance at the output. In fact, there is a limit to how much I should put. recommendation suggests these 22uF caps at the output but I also added 47uF elec. caps to have extra bulk capacitance since it is well within the upper limit.

Quote
The 3.3 and 5V outputs seem reasonably well filtered near the connector, but V12 is not at all.  But the input is heavily filtered (but only differential mode).

kindly explain differential mode filtering you mentioned.

12v input is itself the 12v rail. it is heavily filtered but unfortunately doesn't seem to have done what I hoped. the third party PSU has 33uH inductors with 100uF elec.caps output filters after regulators... it gets nearly the same result.

do you mean I must put big caps near the 12v output connector pin itself? but the signal is very well filtered before and the trace is thick and not too long to cause all this.

Do you find it applicable to remove all that 200-260mV p-p ripple and noise from the 12v input? especially for 3.3v and 5v rails (and 12v one as well).

Should I go for 33uH or similar very big inductance with elec. caps to filter the 12v? since my inductors are very small.

I say this assuming that if the buck regulators are fed with very clean 12v signal, they won't add ripple and noise to it as they claim since we concluded that the input ripple and noise will be suppressed but still get in if not filtered.



___

Quote
chip operated at 1-2Mhz,  radio frequency , extremely short connections,  filled ground, dual side for ground, shielding, etc

I did make connections short, could be shorter too. You mean I have to make top and bottom layers as ground fills?

Quote
pdf define a spec even for caps, due to freq. and resistance.

passives are all cheap from LCSC, didn't get low ESR or so but rather suitable footprint and voltage.

Quote
huge caps or L doesn't help much due to freq.  find caps - freq. dependence graph.

Input frequency is not high, so I assume big caps cap be good right? what about putting higher amount of inductors like 220~470uH as LC input filters, multistages?

how can I get the low noise\ripple factor that I require?


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Re: My PSU design ripple and noise with picture measurements
« Reply #9 on: August 25, 2021, 10:23:13 pm »
If anyone interested or can properly measure the ripple and noise of my small board, I can send it to him. Please advise.

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Re: My PSU design ripple and noise with picture measurements
« Reply #10 on: August 26, 2021, 01:00:07 pm »
Why isn't ground poured under everything?  Most especially the regulators themselves, but also contiguously under the board?  Likely the ripple measurement is largely common mode (due to the high ground impedance between connectors)..?

C6-C8, C10 and C12 do absolutely nothing; I don't know where such tiny values came from.  The ferrite beads largely do nothing as well, they saturate under bias (typically >50mA, depends on value and size -- they may still be seen to help out at light loads).

Bleeder/load resistors should not be necessary.  If you are finding instability, check component values, or select a regulator with external compensation so it can be better tuned.

Note that such large ceramics (22uF, in, what are these, 0805s?) run out of capacitance quickly under DC bias, not so much at 3.3V, a bit at 5V, definitely at 12V.  This is probably still fine because of the parallel quantities, but keep this in mind when going from design calculations to component selection.

Since you're using electrolytics (well, polarized something anyway, maybe they're polymer I don't know), I don't get the large quantities of 22uF chips; a couple electrolytics would do as good a job, plus one or two ceramics to "take the edge off".  Otherwise, if you're not squeamish about the cost of so many caps, why not just go all in, who needs electrolytic?  (Except maybe at the input, if there's a need for bulk capacitance say for mains filtering or hold-up time.)

The 3.3 and 5V outputs seem reasonably well filtered near the connector, but V12 is not at all.  But the input is heavily filtered (but only differential mode).

Tim

I thought of your words and guessed that maybe be a simpler approach is better.

Using this 100uH inductor: https://www.digikey.com/en/products/detail/pulse-electronics-power/PA4309-104NLT/5361574 (or cheaper from LCSC).

preceded and followed by 1000uF caps parallel to ground, which acts as 3rd order LC filter.

This would be the only filtration for 12v input rail, then I feed this into the switchers and remove the useless small value ceramic caps and only keep the 22uF ones in both input and output. While also keeping 47uF elec. caps for outputs and add one elec. 47uF + 22uF ceramic + Ferrite bead just before the 12v connector itself.

What do you think?

I could add another stage of 100uH inductor which will take more space and require more 1000uF caps... if it is necessary, but this way I will need to use cheap LCSC inductors instead of that expensive Pulse-electronics one.

I wonder about those designs where people put various ceramic caps values in parallel, especially at output. like 22u, 1u, 100n, 1n... does this really enhance HF noise suppression?

Using this scope at the fablab would be problematic due to the horrible noise floor (tested by shorting the probe to GND pins) of 50mV. Should I use CH1 to get power (3.3v, 5v, 12v) and CH2 for probing GND, then do subtraction in scope software? shouldn't this eliminate the noise floor?

I think I cannot go to market with this design if it is just slightly better than the best one available, I wanted it to be a lot better.

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Re: My PSU design ripple and noise with picture measurements
« Reply #11 on: August 26, 2021, 02:01:34 pm »
Do you know how much filtering you actually need?

100uH is pretty large.  Certainly large enough you need to account for its impedance, so as not to make the supplies "bouncy".  Too high of an impedance into a switching regulator, at a low frequency, and you get an oscillator -- the regulator input is negative resistance (it doesn't need to draw as much current, at higher voltage, since it conserves power).

Note that a supply isn't just, you stick a filter on it and it's done.  Filtering is with respect to a given connection.  If the input isn't noisy, you might simply wire the 12V input to the output connector and that's that.  The regulators are a pretty obvious source of noise, so it makes sense to add a filter between regulator input, and power input or output.  This is why I noted the 12V output is unfiltered: it carries full regulator ripple to the output.


<snip>
This would be the only filtration for 12v input rail, then I feed this into the switchers and remove the useless small value ceramic caps and only keep the 22uF ones in both input and output. While also keeping 47uF elec. caps for outputs and add one elec. 47uF + 22uF ceramic + Ferrite bead just before the 12v connector itself.

What do you think?

Yes, that sounds fine, or at least more reasonable; exact values still matter so it depends, but that should be in the right ballpark.

Again, ferrite beads amount to nothing; it's strange that they're even shown in the regulator datasheet at all, but it's also amusing that they label it as "10nH", i.e., as good as an equivalent length of wire (well, a cm or so).

If you know you need some actual output filtering, more like 0.1 to 2.2uH is probably reasonable, plus enough capacitance to get Zo low enough for required load step response, and well damped so it doesn't oscillate.

Zo = sqrt(L/C) is the characteristic impedance of an LC circuit.  When Zo ~ R, the network is well damped.  (Whether it's greater or lesser by a modest factor (say 1-2x), depends on how it's arranged.)  Zo gives the step response, as a load step change of say 1A is expected to develop Zo*1A peak voltage change.  If your output is say 3.3V 1A, and regulation must be within 5% including transients, then peak voltage must be under 0.165V for a full load step or 1A change, so Zo < 0.165Ω.

For 1uH and Zo < 0.165Ω, C > 36.7uF.  This can be, for example, a 22uF ceramic in parallel with 47-100uF electrolytic, selected for ESR ~ 0.15Ω.  Or the equivalent constructed from parallel ceramics and an explicit resistor.

Or if using just ceramics, since ESR ~ 10mΩ on those, you need Zo similarly low, say L around... 10nH?  Well, I suppose that explains where that number came from.  Note that 10nH and 22uF has a cutoff of 340kHz so will not attenuate much more than the sheer bulk capacitance is already doing.  Which makes sense, the caps themselves have 2-3nH ESL so a 10nH in series between a few of them doesn't really mean anything, it's a pretty weak impedance divider, hardly a filter at all.

Quote
I wonder about those designs where people put various ceramic caps values in parallel, especially at output. like 22u, 1u, 100n, 1n... does this really enhance HF noise suppression?

At best, it's an outdated practice.

The ESL of a chip capacitor is essentially its package size.  Period.  It hardly depends on value, it doesn't depend on voltage, it depends a bit on height, and most of all it depends on the length and aspect ratio.  (Which is why wide-body components are recommended for critical applications.)

The frequency of minimum impedance (series resonance) does depend on value, but the asymptote extending above there, is the same impedance -- the same ESL -- regardless of value.

So you get as good performance, beyond say 10MHz, with 0.33uF as with 33uF or anything inbetween.

Putting smaller caps in parallel, is likely to make things worse, due to the resonant loop formed between the smaller cap, its capacitance, and the larger cap.  Such loops are on the order of 6nH, so for say a 10nF, you get Zo = 0.77Ω and Fo = 20MHz.  The 10nF might have 100mΩ ESR, giving a Q of 7, or an impedance peak (parallel resonant equivalent, Zpeak = Zo * Q) of 5.4 ohms -- massively worse than the impedance of the bulk cap's inductance alone (which if it's 3nH, is only 0.377Ω at 20MHz).

And for switching regulators, it's not likely to do much of anything at all, anyway: the impedance is so much lower than for an individual logic IC for example.  Say the peak voltage and current are 12V 2A, then the impedance needs to be much less than their ratio, or 6Ω.  A small cap like 10nF just disappears, it does nothing, the input ESL dominates.  Much better to put the bulk cap there, or at least a big enough bypass (typically 1uF) to dominate over the ESL to the next bigger cap (while again being chosen for ESR to dampen that loop!).

So a 1uF at each regulator, and one or a few 22uF nearby, is likely fine for your purposes.  Plus whatever input filtering is needed, again dimensioned so that Zo is low enough, and with ESR provided to dampen it.


Quote
Using this scope at the fablab would be problematic due to the horrible noise floor (tested by shorting the probe to GND pins) of 50mV. Should I use CH1 to get power (3.3v, 5v, 12v) and CH2 for probing GND, then do subtraction in scope software? shouldn't this eliminate the noise floor?

I think I cannot go to market with this design if it is just slightly better than the best one available, I wanted it to be a lot better.

What?  You mean the scope, probe disconnected, has a noise floor that high?  It sounds defective.

If you mean with the probe tip grounded to its clip, and this point connected to circuit ground, then that is probably typical of your circuit's common mode noise, and this is dropped across the narrow, lengthy ground return path around the regulators.  And will likewise be emitted from the power cable, failing EMC.

They don't show the bottom layer in the datasheet layout example, but one should assume it's ground pour.  They do show vias for this purpose.  Strangely, they also show vias for VIN and VOUT, which have no business running on the bottom layer.  It's not clear what they mean by that.  Examples must always be taken as just that, examples; sometimes they're reasonable, sometimes they're cooked up by some random intern, who knows.

Another tip: avoid VIN and VOUT on opposite sides of the board -- this guarantees that, the full voltage drop across circuit ground, appears between connectors.  Instead, place them adjacent where possible, and route the connections over to the regulators, off to the other side.  This confines ground-loop currents to the regulator area.  Routing VIN and VOUT away from that critical area, they can be filtered with respect to a more stable GND, with less voltage drop between their respective GND connections (namely, the filter cap GNDs).

Tim
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Re: My PSU design ripple and noise with picture measurements
« Reply #12 on: August 26, 2021, 07:05:53 pm »
Quote
Do you know how much filtering you actually need?

I don't know exactly but I know it needs good amount of it, switching regulator wall PSUs used are noisy.

Quote
100uH is pretty large.

I know but it seems enough to eliminate all that. most of these PSU used and to be used are in the low frequency range, certainly less than 1 MHz. Please refer to previously shown images to see input and output waveforms on the scope.

Quote
Again, ferrite beads amount to nothing; it's strange that they're even shown in the regulator datasheet at all, but it's also amusing that they label it as "10nH", i.e., as good as an equivalent length of wire (well, a cm or so).

their idea is that ferrite bead is integrated within the feedback loop itself, which is their new solution to achieve very low noise figure as shown in their datasheet and videos. it is not just an output filter.

Quote
Zo = sqrt(L/C) is the characteristic impedance of an LC circuit.  When Zo ~ R, the network is well damped.  (Whether it's greater or lesser by a modest factor (say 1-2x), depends on how it's arranged.)  Zo gives the step response, as a load step change of say 1A is expected to develop Zo*1A peak voltage change.  If your output is say 3.3V 1A, and regulation must be within 5% including transients, then peak voltage must be under 0.165V for a full load step or 1A change, so Zo < 0.165Ω.


Assuming 100uH + 1000uF, Zo = 0.316 according to equation and this site: http://circuitcalculator.com/lcfilter.htm ... this is without 1000uF before the inductor, only after it. So it is 1 inductor and 1 capacitor solution.

3.3v will be 2.8~3A full load while 5v is only 0.5A (could go a bit more). 12v is not really used for anything but GD drive motor if it is still installed, so very little current.

I didn't quite understand load step requirement you posted, kindly inform me.

The system is 22 Watts, I assume 25W PSU. 12v will be 2~2.5A, 3A at beyond max. so 12/2 = 6 Ohms or 12/3 = 4 Ohms. Z = 100uH/1000uF = 0.32 Ohms. This is for 12v input only, which is both input to the 2 regulator rails and an output of 12v for the system.

the regulators, say the 3.3v one is said to be 3 amps. 3A * 5% = 0.15v , now 0.15V/3A = 0.05R. Is this what you meant back then? Now this has nothing to do with 12v heavy filtering I talked about... please notice that the switching regulators circuit will not change by much if any... I was talking about 100uH 1000uF for the 12v input filtering only.

I already pointed out that TI specified a number of total output capacitance limit, and I adhere to it. putting 3x22uF ceramics + 1 47uF elec. seems good enough. having 3x22uF ceramics as input filtering for the regulators (fed from the heavy filtered 12v) is also suitable to datasheet.

Our whole point here is that the input noise and ripple is passing through to the output 3.3v and 5v despite using great quality switcher. therefore, the conclusion was that the switcher needs clean input to be able to provide its clean output... therefore, we will clean the 12v using heavy filtering.

Quote
The ESL of a chip capacitor is essentially its package size.

Ok, so using 22uF 0805 seems good enough.

Quote
If you mean with the probe tip grounded to its clip, and this point connected to circuit ground, then that is probably typical of your circuit's common mode noise, and this is dropped across the narrow, lengthy ground return path around the regulators.  And will likewise be emitted from the power cable, failing EMC.

Yes, probe is connected to ground and shows 50mV p-p. It is not just my own circuit but the third-party PSU as well. this PSU uses 33uH + 100UF filtering for both rails output but of course using a traditional cheap and available generic switcher.

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Re: My PSU design ripple and noise with picture measurements
« Reply #13 on: August 29, 2021, 11:23:53 pm »
"The ferrite beads largely do nothing as well, they saturate under bias (typically >50mA, depends on value and size -- they may still be seen to help out at light loads)."

"Again, ferrite beads amount to nothing; it's strange that they're even shown in the regulator datasheet at all, but it's also amusing that they label it as "10nH", i.e., as good as an equivalent length of wire (well, a cm or so)."

I don't get this statement at all. The wurth 74279221100 mentioned in the datasheet takes a LOT of current to saturate.

https://www.mouser.com/datasheet/2/445/74279221100-1720641.pdf

Still 10 ohms at 100 MHz at 5 amps.
 

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Re: My PSU design ripple and noise with picture measurements
« Reply #14 on: August 30, 2021, 01:15:15 am »
No, I didn't look at the exact part.

Indeed that one handles quite a lot of current; and they actually provide curves -- a welcome sight!

In fact they show closer to 14nH, an absolute bounty in there! :-DD :-DD


OP didn't write down a part number or provide BOM so it's not clear if they're using same.

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Re: My PSU design ripple and noise with picture measurements
« Reply #15 on: August 30, 2021, 08:45:44 am »
No, I didn't look at the exact part.

Indeed that one handles quite a lot of current; and they actually provide curves -- a welcome sight!

In fact they show closer to 14nH, an absolute bounty in there! :-DD :-DD


OP didn't write down a part number or provide BOM so it's not clear if they're using same.

Tim

I have used this one: https://www.murata.com/en-global/products/productdetail?partno=BLE18PS080SN1%23

which is recommended in the datasheet of TI.

Key BOM items:

4.7uH inductors: https://lcsc.com/product-detail/Inductors-SMD_PSA-Prosperity-Dielectrics-MCS0630-4R7MN2_C385253.html ...

although in my previously made units I used PA4340.472NLT which was similar to recommended ones (XGL4030-472). I assumed that getting a cheap one will work and it did, but not sure its effect on noise performance. I plan to test my previously made units on the scope this time. Their only issue was a slightly more increased voltage on 5v, around 5.2v which made me change the values then I took the chance to add more filters..etc

22uF ceramic caps: https://lcsc.com/product-detail/Multilayer-Ceramic-Capacitors-MLCC-SMD-SMT_SAMSUNG_CL21A226MAQNNNE_22uF-226-20-25V_C45783.html

1uH inductor: https://lcsc.com/product-detail/New-Quadratic-Unclassified-Data_GLE-GCDA252012P-1R0MC_C439318.html

1000uF elec. cap: https://lcsc.com/product-detail/Aluminum-Electrolytic-Capacitors-SMD_Lelon-VE-102M1CTR-1010_C249474.html


____

What can be done to enhance the performance?

Anyone can kindly volunteer to test the 2 units (new and old)? I can send it via mail since I don't have a scope now and it will be very hard to do measurements.

My current thought is to have a 2-stage LC filter of say 100uH+1000uF in each stage... or 47uH+1000\2200uF or similar... for the 12v input, then for 12v output connector itself I can put another 1000uF cap.

I am not fond of the idea to replace the 22uF ceramics by elec. caps. datasheet wants ceramics especially for output which I added a 47uF elec. cap as an added filtration.

___

TPS62913 stated > 65 dB PSRR for <100 Khz which I didn't take into account. So assuming 200mV p-p actual noise and ripple (after taking off 50mV noise floor), I got 10-40mV final output (after taking off 50mV noise floor)... is that what this 65 db PSRR suggests?

Offline T3sl4co1l

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Re: My PSU design ripple and noise with picture measurements
« Reply #16 on: August 30, 2021, 05:23:53 pm »
Those components seem fine.

The ferrite bead does not provide DC bias characteristic (Murata doesn't record it for any ferrite beads at all, I'm pretty sure) but given the other part above, it's probably fine around an ampere or so.  And, again given the value, it's doing very little in any case.

The 22u caps don't have a char sheet, at least that I saw from a glance.  Huh, they're also listed as obsolete at other suppliers, I wonder where LCSC is getting them......

Note that both (cored) inductors, and type 2 ceramic caps, lose value under bias (current and voltage respectively).  You get a 22uF cap at 0V; at 12V it's probably like 3uF or so.  Still enough to be useful, but keep this in mind when designing filters, and prefer parts with actual characteristics.

X5R is also a bit on the low side, but it shouldn't be too much worse in terms of voltage dependency or tempco compared to X7R or better, as long as you aren't operating at high temperatures (the 5 means 85°C max, 7 is 125).  Note that temp rise (power dissipated in ESR) can be relevant for caps handling high ripple currents -- probably not here, but can be important for bigger converters (100s watts?).

PSRR is Power Supply Rejection Ratio.  That is, how much does the output voltage change, for a given change in input voltage.  For example, suppose a buck converter operates at a fixed PWM: Vo = Vin * D (D = duty cycle).  In this case, PSRR = -20 * log(D), because say 1V changes at the input, and D is 0.5, then the output changes by 0.5V and the PSRR is 6dB.  And this will be true for frequencies from DC up to the cutoff frequency of the input and output filters, where filter attenuation dominates (and thus PSRR goes up: PSRR = filter attenuation - converter gain).  It's improved still further by the control circuit, varying D to maintain Vo.  This gives high PSRR at DC, up to the error amp's cutoff frequency more or less; at which point the filters should take over.  And with >65dB PSRR overall, it sounds like this is the case for their design.  Put another way, the output is disturbed by less than one-thousandth the input change (20 log(1000) ~= 60dB), a generally excellent figure.

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Re: My PSU design ripple and noise with picture measurements
« Reply #17 on: August 30, 2021, 06:29:03 pm »
So why I am not getting the performance I expected? I mean, the input to the switchers should already be very clean in order for them to make a clean output right? therefore we need to heavily filter the 12v rail.

any suggestions besides those of my previous reply?

I picked cheap and suitable parts from LCSC without much hassle about characteristics. I cared about ceramic caps to be of high voltage, bigger package (for bias stuff), and a 22uF value. ferrite beads after the switchers are essential since they are part of the control loop itself and necessary to give very low output noise and ripple. FB on inputs and 12v is my own doing.

I am open to your suggestions.

Offline T3sl4co1l

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Re: My PSU design ripple and noise with picture measurements
« Reply #18 on: August 30, 2021, 09:03:33 pm »
The problem is not so much the filter topology, it's the ground topology.  Consider what you would measure in a circuit such as this:



L2 might be quite small, say 10nH, but it is not at all irrelevant.

Consider further the equivalent circuit of your scope probes making connection to this circuit.  The ground clips have some inductance (fraction of a uH) up to the probe body not coupled with the probe tip, and the cables have some inductance between them (~1uH), looping through scope ground (and mains as applicable).  Thus the probes have an inductance divider equivalent circuit, where the ground clip draws current corresponding to the inductance between probes, and the voltage dropped by the clip is not sensed by the probe tip (but the rest of the cable is reasonably shielded, i.e. the signal and shield are well coupled).

This voltage is most apparent when probing with the tip attached to the ground clip, the combination being poked against various (mostly / hopefully "ground") points in the circuit; a null result shows no common mode noise with respect to the oscilloscope (presumably, whatever power supply / ground return path is shared by the power supply and scope), a non-null result shows there is voltage being dropped across this or other loops.

And this common-mode voltage cannot be filtered by taking on more LC stages, which accomplish only differential filtering.  There is another mode!


The best remedy is to put the connectors to one edge, solid ground pour (top and bottom, with adequate via stitching), over all, and regulators to the other (far) edge.  This shorts the connector grounds together, while putting distance between the critical switching loop(s), and minimizing the value of L2 (it can be a few nH in a good layout), and its size (some mm across), thus its fields drop off rapidly with distance.  And the connectors (and their respective filters) are placed at a distance from the regulator, keeping them well clear of that noise.

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Re: My PSU design ripple and noise with picture measurements
« Reply #19 on: August 31, 2021, 02:22:50 am »
Even if it is a small inductor, doesn't the real impedance help with de-Qing your filter? I mean, I might just ask in what situations you see ferrites being useful.
 

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Re: My PSU design ripple and noise with picture measurements
« Reply #20 on: August 31, 2021, 02:58:57 am »
I would try smaller capacitance (4.7 uF, 10 uF) but larger case X7R caps (1206, 1210) instead of 22 uF 0805 caps, possibly several in parallel.
And the topology of an input cap on the PCB has a very large influence on the overall noise too. It must be very close to the noisy part. The PCB topology means much more than the C value (when we are talking about low-noise design)
« Last Edit: August 31, 2021, 03:11:14 am by Vovk_Z »
 

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Re: My PSU design ripple and noise with picture measurements
« Reply #21 on: August 31, 2021, 07:57:58 am »
Even if it is a small inductor, doesn't the real impedance help with de-Qing your filter? I mean, I might just ask in what situations you see ferrites being useful.

the ferrites are part of tps62913 circuit feedback loop. they are necessary to reach that very low noise and ripple figure. However, ferrites at input side of 12v is my own idea which I am not sure if it helps or not.

You talked about real impedance of L, I don't know the exact value but if damping is required then I can put a resistor in series with a 22uF capacitor but this value I read it should be very low, meaning like 0.3 ohms or a bit more... this is not hard. I could also put elec. caps to help damping it with their higher ESR.

My concern is killing the 12v noise and ripple first. This is why I got the idea of having big inductor like 100uH with 2 1000/2200/4700uF caps at the 12v source. then the inputs to the switchers are very easily done via ceramics. what about this idea? what could go wrong with these huge L and C values in terms of stability and effectiveness?

Quote
I would try smaller capacitance (4.7 uF, 10 uF) but larger case X7R caps (1206, 1210) instead of 22 uF 0805 caps, possibly several in parallel.
And the topology of an input cap on the PCB has a very large influence on the overall noise too. It must be very close to the noisy part. The PCB topology means much more than the C value (when we are talking about low-noise design)

switchers require 22uF caps, but I think I can fit a slightly bigger cap size of 1206 if I try harder.

Are you talking about the 12v rail or the switchers? shouldn't a big 47uH/100uH inductor with 2x of say 2200uF caps (before and after or just after) be able to filter out the ripple and noise? the cut-off frequency will be small and will attenuate a lot of the 250mV p-p of the input.

I figured that the switchers need clean input in order to give the clean output. they have > 65 dB PSRR for frequencies < 100 KHz which is good but still not good enough to eliminate 200mv p-p noise and ripple, therefore I would need to make it a lot less.

Quote
The best remedy is to put the connectors to one edge, solid ground pour (top and bottom, with adequate via stitching), over all, and regulators to the other (far) edge.  This shorts the connector grounds together, while putting distance between the critical switching loop(s), and minimizing the value of L2 (it can be a few nH in a good layout), and its size (some mm across), thus its fields drop off rapidly with distance.  And the connectors (and their respective filters) are placed at a distance from the regulator, keeping them well clear of that noise.

So I could just make bottom layer all one ground, but top layer has to have power pours for each switcher as seen in datasheet... but every other place can be GND pour with many vias to stitch it.

You mean I should re-arrange the board to have 12v input in top with its LC filter followed by the switchers circuit which is tight and compact. no distance needed between the 12v and switchers? then just send the 3.3v and 5v regulated rails to output connectors? this would mean long distance for them.

Or maybe put the switcher circuit close to the connector with its filter caps very close to output connectors while all this is far from 12v circuit?

Quote
T3sl4co1l

Do you mind if I sent the board to you? to do some scope measurements the proper way and so on. this will really help me.

Offline T3sl4co1l

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Re: My PSU design ripple and noise with picture measurements
« Reply #22 on: August 31, 2021, 03:40:11 pm »
Even if it is a small inductor, doesn't the real impedance help with de-Qing your filter? I mean, I might just ask in what situations you see ferrites being useful.

Mind these aren't simply miniature ferrite beads like you're used to; the impedance is largely imaginary up to, what was it, 300, 500MHz?  The peak impedance is in the GHz.  They're actually pretty good inductors at those lower frequencies.

As I demonstrated earlier, the advantage is building a filter against the very low ESR of the ceramic caps.  The disadvantage is the Fc is very high, doing an okay job of filtering harmonics and a poor job of fundamental (Fsw) ripple.


the ferrites are part of tps62913 circuit feedback loop. they are necessary to reach that very low noise and ripple figure. However, ferrites at input side of 12v is my own idea which I am not sure if it helps or not.

You've repeated this several times, but you're simply quoting from the datasheet, no?  Do you understand in what way they are necessary, and to what extent they function?

Without any understanding of the regulator's internal characteristics, I am confident to say that, if I merely sat down with an eval board and a handful of assorted filter components, I would be able to improve the input and output noise characteristics by a hundredfold.  (Or by perhaps 1k to 10k times, in case of your original example -- I would need some additional materials then, to build a shield around the PCB, to avoid the ground-loop issue.)

You can give this a spin, yourself, I think, on TI's WEBENCH simulator.  They should have a full-enough model of this part, and enough flexibility to implement a variety of filter types.  It may even design them for you, and simulate the likely ripple -- again, assuming ground-loop voltage is avoided.

The biggest key is likely using a bulk cap (capacitance several times the surrounding (low-ESR) capacitance (C), with ESR = sqrt(L/C), L being the filter inductor(s)).  This "de-Qs" the filter, as ezalys hinted at.  Other terms: damping, snubbing, terminating.

A filter is an impedance network, and just like a transmission line, it must operate into a terminated load resistance; it just happens that its characteristic impedance is low (for typical power supply applications), and so will be the resistance needed for it.  And, since we want to pass DC without shorting it, we put a coupling capacitor in series with the resistance, and as a coupling capacitor, it simply needs enough capacitance so that it's largely resistive at the frequencies relevant to the filter (namely the transition band of the filter, Fc = 1 / (2 pi sqrt(LC)) give or take say a factor of 2).


Quote
You talked about real impedance of L, I don't know the exact value but if damping is required then I can put a resistor in series with a 22uF capacitor but this value I read it should be very low, meaning like 0.3 ohms or a bit more... this is not hard. I could also put elec. caps to help damping it with their higher ESR.

So, exactly this; but not just one, it will be dominated by the others in parallel; the balance must be more like 1 alone versus 2 or 3 with ESR.  So it's kind of inefficient to do this with ceramic caps plus external resistor, and electrolytic or tantalum are often preferred.


Quote
My concern is killing the 12v noise and ripple first. This is why I got the idea of having big inductor like 100uH with 2 1000/2200/4700uF caps at the 12v source. then the inputs to the switchers are very easily done via ceramics. what about this idea? what could go wrong with these huge L and C values in terms of stability and effectiveness?

More likely 0.1 to 4.7uH is more than sufficient, and such large values aren't necessary.  You have very little to gain, I think, from going to any larger value.


Quote
I figured that the switchers need clean input in order to give the clean output. they have > 65 dB PSRR for frequencies < 100 KHz which is good but still not good enough to eliminate 200mv p-p noise and ripple, therefore I would need to make it a lot less.

Excuse me, do you understand what 65dB represents?

The observed noise isn't at <100kHz anyway, I'm willing to bet.  All the more reason why filtering is needed, but also why common mode filtering is critical.


Quote
So I could just make bottom layer all one ground, but top layer has to have power pours for each switcher as seen in datasheet... but every other place can be GND pour with many vias to stitch it.

Yes!

The power pours can be smaller; they don't need to be much bigger than the chip, really, and that's all they show in the datasheet anyway.  Around them, can be filled with GND.


Quote
You mean I should re-arrange the board to have 12v input in top with its LC filter followed by the switchers circuit which is tight and compact. no distance needed between the 12v and switchers? then just send the 3.3v and 5v regulated rails to output connectors? this would mean long distance for them.

Connectors, plural.  All of them.  If you can't physically move the 12V input down to the bottom edge, then route it down along its side, over by the outputs, and place its filter there.  Slot the ground pour beside this route, so that any ground loop currents by the regulators, do not bypass the filter and jump into the 12V connector directly.

DO NOT ROUTE TRACES OR POWER POURS OVER A GROUND SLOT.


Quote
Do you mind if I sent the board to you? to do some scope measurements the proper way and so on. this will really help me.

Honestly I don't think it will make much difference.  And the grounding problem is not an easy one to solve by hand, even with heroic effort (cutting and patching pours!).

Also, you have some lingering questions about the quality of your source power supplies, I think.  You should evaluate those as well.

What I think would be much more valuable, is simply iterating the layout.  Layouts are cheap.  If it took you a long time to build the first one, I can understand your hesitance, but appreciate that it will go faster each and every time after, as you gain familiarity with the tools, and begin to understand the current flow paths.  We've spent far, far more time in this thread, than it would take an experienced designer to re-lay the entire circuit.  And proto PCBs are cheap to order, unless you're strapped for cash of course, in which case all the more reason to get it right the first time.

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Offline Vovk_Z

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Re: My PSU design ripple and noise with picture measurements
« Reply #23 on: August 31, 2021, 03:54:55 pm »
Are you talking about the 12v rail or the switchers? shouldn't a big 47uH/100uH inductor with 2x of say 2200uF caps (before and after or just after) be able to filter out the ripple and noise? the cut-off frequency will be small and will attenuate a lot of the 250mV p-p of the input.

I figured that the switchers need clean input in order to give the clean output. they have > 65 dB PSRR for frequencies < 100 KHz which is good but still not good enough to eliminate 200mv p-p noise and ripple, therefore I would need to make it a lot less.
Yes, I'm talking about an input (12VDC side) cap. The main thing is rather not to filter, but to make low-impedance low-area input loop. 2200 uF or even 22 0000000 uF caps won't help, but 1 uF well-placed may do the job.
Your DC-DC has some PSRR so it doesn't need very "clean input". The purpose of input filter is not to filter an input voltage, but rather to isolate your DC-DC from other circuit. It filters spreading a generated noise into other area through input.
« Last Edit: August 31, 2021, 04:03:08 pm by Vovk_Z »
 

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Re: My PSU design ripple and noise with picture measurements
« Reply #24 on: August 31, 2021, 05:22:21 pm »
Quote
You've repeated this several times, but you're simply quoting from the datasheet, no?  Do you understand in what way they are necessary, and to what extent they function?

I didn't dig into this much tbh, but they keep repeating it as their way to achieve that very low noise\ripple figure. Also, as you mentioned, the FBs won't do anything bad if by any chance they didn't do good. I don't think they are the problem here, do you?

Quote
You can give this a spin, yourself, I think, on TI's WEBENCH simulator.

I will try that sometime soon I hope. But maybe it is not accurate since it may not include the type of noise from source.

Quote
The biggest key is likely using a bulk cap (capacitance several times the surrounding (low-ESR) capacitance (C), with ESR = sqrt(L/C), L being the filter inductor(s)).  This "de-Qs" the filter, as ezalys hinted at.  Other terms: damping, snubbing, terminating.

you mean the 12v input side LC filter? it does have 1000uF elec. cap at the end but not directly after the main 4.7uH inductor.

Or you mean the input to each switcher? there I can put 2 47uF elec. caps in parallel plus say 2 22uF ceramics and one 2.2nF to be closest to the IC pin as requested in datasheet. How about that? putting 1000uF instead of the 2 47uF ones or instead of one of them is doable too but needs a lot of rearrangement.


Quote
More likely 0.1 to 4.7uH is more than sufficient, and such large values aren't necessary.  You have very little to gain, I think, from going to any larger value.

I already have 4.7uH since I used it in the switchers circuit. as you see, it is followed by other 1uF ones in series plus the caps..etc.

However, is putting a larger (47uH) inductor will make it bad? notice that the 12v input sources are assumed to be bad in terms of ripple and noise... one source could have little noise\ripple and another one is large ripple..etc. this design is done assuming the people get any reasonably-good 12v 3amps wall-adapter and it should work fine.

Quote
The observed noise isn't at <100kHz anyway, I'm willing to bet.  All the more reason why filtering is needed, but also why common mode filtering is critical.

You don't need to bet, I posted pictures with this reply to show 12v input, 3.3v output, and 5v output for both MYPSU and OTHERPSU as label suggests. Looks like frequency of the ripple is a lot less than expected which should be attenuated better IMO. I think with pictures you can judge better.

Notice that ground probing sometimes shows 100Hz and sometimes > 800Hz... I posted the picture of 800Hz but from waveform you can judge better.

Quote
Connectors, plural.  All of them.  If you can't physically move the 12V input down to the bottom edge, then route it down along its side, over by the outputs, and place its filter there.

I am afraid 12v input and its switch connector have to be on top.

Can't I put it in top along with its filters then put close vias to GND for each cap?

also, will the switchers and their circuit be near the 12v connector and filters?

if so, then your idea is to make the output connector very far from the actual switching loop... with bulk caps near the output connector itself rather than the switchers?


Quote
Yes, I'm talking about an input (12VDC side) cap. The main thing is rather not to filter, but to make low-impedance low-area input loop. 2200 uF or even 22 0000000 uF caps won't help, but 1 uF well-placed may do the job.
Your DC-DC has some PSRR so it doesn't need very "clean input". The purpose of input filter is not to filter an input voltage, but rather to isolate your DC-DC from other circuit. It filters spreading a generated noise into other area through input.

Hmmm so you agree with T3sl4co1l on the ground pour, and with me on putting short and close ground vias to caps of input filter and switcher circuit?

still, big LC values are better than small ones for 12v rail... due to different quality of input sources. So, isolating the DC-DC switchers from input 12v is done via good routing and making very short loops... plus, making output connector with its caps far from switcher loop itself. correct?

Do you honestly think we can match the < 1mV p-p output capability of the switcher by doing this?

thanks all for your help, I am willing to enhance the design as much as I can.


_________

as for making another board.. it is not cheap since it needs machine setup and so on. I even got a good discount from allpcb this time.

I can however, use JLC PCB very cheap service which has everything from inductors and caps but it doesn't have that particular ferrite bead and of course the TPS62913 chip which is extremely small.. I don't have much confident I could desolder it from the current boards then re-solder it on the cheap jlcpcb produced board.

Offline Vovk_Z

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Re: My PSU design ripple and noise with picture measurements
« Reply #25 on: August 31, 2021, 07:38:40 pm »
I can't say anything about ground pour. It's a subject which is better to investigate with a real PCB on hands. I'm not as experienced to give all the answers via the internet, unfortunately. There may be Application notes covering this topic for other similar ICs.
 

Offline iMo

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Re: My PSU design ripple and noise with picture measurements
« Reply #26 on: August 31, 2021, 09:00:13 pm »
I would highly recommend you to start with LTSpice simulator, for example (it is free and you may get help here).
You should put all your parasitics (ie. the trace inductance L2 in Tim's schematics above, as an example), inlcusive RLC of your capacitors and inductors, resistance/inductance of your pcb tracks, etc.

I've done similar exercise recently - where on the o'scope I saw 3Vpp ringing instead of a clean signal. I did a simulation with my real 20mm long wires (20nH parasitic inductance) and I got exactly the same picture in the LTSpice.
Thus instead of excessive soldering and elaborating do spend more time with simulation, it works.

Also - a filter made of 100uH and 1000uF would work perfectly on a paper, in reality not so - see below your low pass (the values are examples only)..

« Last Edit: August 31, 2021, 09:01:52 pm by imo »
 

Offline T3sl4co1l

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Re: My PSU design ripple and noise with picture measurements
« Reply #27 on: August 31, 2021, 09:01:07 pm »
You know what the fuzzy waveforms mean, right?  :) Zoom in until you see smooth curves.  There's high frequency noise that's merely riding on, or modulated by, those low frequencies.

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Offline thm_w

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Re: My PSU design ripple and noise with picture measurements
« Reply #28 on: September 01, 2021, 12:15:26 am »
gofundme for OP to get a decent starter oscilloscope?
 :D
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Re: My PSU design ripple and noise with picture measurements
« Reply #29 on: September 01, 2021, 10:09:24 am »
You know what the fuzzy waveforms mean, right?  :) Zoom in until you see smooth curves.  There's high frequency noise that's merely riding on, or modulated by, those low frequencies.

Tim

What is your opinion on the actual waveforms I posted in my latest reply? they show everything... I hope we can understand the problem from them. what shocked me is that the frequency is very little < 100 Hz, what is going on?

Right now, the to-do solution is better routing and grounding, plus to see which values of CLC circuit to put + input filters to switchers.

I am interested on your analysis of waveforms of scope.

Offline xavier60

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Re: My PSU design ripple and noise with picture measurements
« Reply #30 on: September 01, 2021, 11:53:46 am »
You know what the fuzzy waveforms mean, right?  :) Zoom in until you see smooth curves.  There's high frequency noise that's merely riding on, or modulated by, those low frequencies.

Tim

What is your opinion on the actual waveforms I posted in my latest reply? they show everything... I hope we can understand the problem from them. what shocked me is that the frequency is very little < 100 Hz, what is going on?

Right now, the to-do solution is better routing and grounding, plus to see which values of CLC circuit to put + input filters to switchers.

I am interested on your analysis of waveforms of scope.
The 100Hz modulation is likely caused by the bridge rectifier at the mains input of a SMPS. Because the diodes conduct only at the mains waveform's peaks, they act as switches that conduct switching noise.
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Offline Vovk_Z

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Re: My PSU design ripple and noise with picture measurements
« Reply #31 on: September 01, 2021, 12:14:35 pm »
what shocked me is that the frequency is very little < 100 Hz, what is going on?
Low frequency oscillation is a feedback instability. It happens in some voltage-current modes. There can be application note how to get rid of them (may not).
I've seen such a thing in one of my DC-DC modules with XL4016, there was found a decision on the internet, to use C or RC-circuit in parallel to IC feedback resistor. I played with it and finally used 10 nF cap in parallel to feedback resistor.
« Last Edit: September 01, 2021, 01:01:06 pm by Vovk_Z »
 

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Re: My PSU design ripple and noise with picture measurements
« Reply #32 on: September 01, 2021, 12:26:48 pm »
Hmmm so you agree with T3sl4co1l on the ground pour, and with me on putting short and close ground vias to caps of input filter and switcher circuit?
Experience I have: I have low-noise DC-DC (with XL4016) with less then 1 mV RMS noise and I didn't use large ground pour. Design was made with wide printed wires which go somewhere near each other, more or less close to each other.
 

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Re: My PSU design ripple and noise with picture measurements
« Reply #33 on: September 01, 2021, 12:35:24 pm »
still, big LC values are better than small ones for 12v rail... due to different quality of input sources. So, isolating the DC-DC switchers from input 12v is done via good routing and making very short loops... plus, making output connector with its caps far from switcher loop itself. correct?
Big L values everywhere except main switcher L may worsen stability but not help. That's one of the reasons you are told not to use large L values.
For example, it you decide to add post-filter after switcher with large L - it will provoke instability. And similar things may happen with unlucky L before the switcher. A typical 'safe' post-filter L value may be no more than 10-20% of a main switcher L.
 

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Re: My PSU design ripple and noise with picture measurements
« Reply #34 on: September 01, 2021, 12:39:32 pm »
Quote
The 100Hz modulation is likely caused by the bridge rectifier at the mains input of a SMPS. Because the diodes conduct only at the mains waveform's peaks, they act as switches that conduct switching noise.

there are no AC on board, I use 12v laptop-style SMPS. It works perfectly fine in terms of continuous operation without issues, I played Dreamcast using it for hours and hours.

Quote
there was found a decision on the internet, to use C or RC-circuit in parallel to IC feedback resistor.

that is called bootstrap capacitor if I am correct, and I have one for each switcher feedback as mentioned in datasheet. Mine is 1uF which is the best value which includes maximum performance (stability, noise cancellation) while being not near the upper limit.


However, if this analysis is correct, it may be coming from the 12v input wall charger itself.

Don't you think some extra input filter elec. caps can help here since it is low frequency?

Quote
Experience I have: I have low-noise DC-DC (with XL4016) with less then 1 mV RMS noise and I didn't use large ground pour. Design was made with wide printed wires which go somewhere near each other, more or less close to each other.

I am interested in this solution if you can explain more or post circuit or methods.


Quote
Big L values everywhere except main switcher L may worsen stability but not help. That's one of the reasons you are told not to use large L values.
For example, it you decide to add post-filter after switcher with large L - it will provoke instability. And similar things may happen with unlucky L before the switcher. A typical 'safe' post-filter L value may be no more than 10-20% of a main switcher L.

Right now I didn't add any but maybe a 1uH is good? assuming the main switcher L is 4.7uH.

That is for post-filter, but why also pre-filter?
____

from my previous waveforms... how much is the actual ripple and noise figure is? how can we know it for sure without the oscillation?


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Re: My PSU design ripple and noise with picture measurements
« Reply #36 on: September 01, 2021, 01:04:46 pm »
Quote
there was found a decision on the internet, to use C or RC-circuit in parallel to IC feedback resistor.
that is called bootstrap capacitor if I am correct, and I have one for each switcher feedback as mentioned in datasheet. Mine is 1uF which is the best value which includes maximum performance (stability, noise cancellation) while being not near the upper limit.
No, I am definitely not talking about bootstrap cap. I'm talking about additional feedback elements (not shown in the datasheet).
 

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Re: My PSU design ripple and noise with picture measurements
« Reply #37 on: September 01, 2021, 01:05:02 pm »
A mains powered SMPS with PFC stage could also possibly produce 100Hz modulated interference.
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Re: My PSU design ripple and noise with picture measurements
« Reply #38 on: September 01, 2021, 01:15:16 pm »
I am interested in this solution if you can explain more or post circuit or methods.
There is nothing interesting to show because the PCB exists in only 'first breed' generation (zero version), but real device have some small changes and improvements made to achieve low noise (<1 mV RMS), made with a knife and wires. So there isn't much sense to show it.
In the attachment I show an additional cap I'm talking about which calmed my switcher.
 

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Re: My PSU design ripple and noise with picture measurements
« Reply #39 on: September 01, 2021, 01:58:00 pm »
I am interested in this solution if you can explain more or post circuit or methods.
There is nothing interesting to show because the PCB exists in only 'first breed' generation (zero version), but real device have some small changes and improvements made to achieve low noise (<1 mV RMS), made with a knife and wires. So there isn't much sense to show it.
In the attachment I show an additional cap I'm talking about which calmed my switcher.

Please check my schematic here.

I understood what it is but failed to remember the name, it is called "feed-forward capacitor" and it is not specific for TPS62913 but rather for all DC-DC converters. I choose 1uF, I wonder if low values such as 2.2nF or your 10nF is better. they claim their low noise performance is done without it.

TPS62913 has also the NR/SS cap which affects soft-start and noise reduction, that too is 1uF.


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Re: My PSU design ripple and noise with picture measurements
« Reply #40 on: September 01, 2021, 03:27:22 pm »
Please check my schematic here.
C22, C23 - 1 uF, really? Why so large value?
 

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Re: My PSU design ripple and noise with picture measurements
« Reply #41 on: September 01, 2021, 03:36:15 pm »
What is your opinion on the actual waveforms I posted in my latest reply? they show everything... I hope we can understand the problem from them. what shocked me is that the frequency is very little < 100 Hz, what is going on?

They show very little, the scale is 25ms and the waveforms are solid blocks of pixels indicating multiple cycles per pixel.  More like 10µs/div would be more interesting.

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Re: My PSU design ripple and noise with picture measurements
« Reply #42 on: September 01, 2021, 03:37:45 pm »
that is called bootstrap capacitor if I am correct, and I have one for each switcher feedback as mentioned in datasheet. Mine is 1uF which is the best value which includes maximum performance (stability, noise cancellation) while being not near the upper limit.
I guess you confused it (C22, C23) with Cnr/ss. This is possibly a root of your low-freq oscillation.
 

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Re: My PSU design ripple and noise with picture measurements
« Reply #43 on: September 01, 2021, 03:40:19 pm »
I choose 1uF, I wonder if low values such as 2.2nF or your 10nF is better. they claim their low noise performance is done without it.
TPS62913 has also the NR/SS cap which affects soft-start and noise reduction, that too is 1uF.
So you haven't tried yet another value for C22, C23 and ask us for a solution?
 

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Re: My PSU design ripple and noise with picture measurements
« Reply #44 on: September 01, 2021, 05:45:18 pm »
I choose 1uF, I wonder if low values such as 2.2nF or your 10nF is better. they claim their low noise performance is done without it.
TPS62913 has also the NR/SS cap which affects soft-start and noise reduction, that too is 1uF.
So you haven't tried yet another value for C22, C23 and ask us for a solution?

I didn't find a value recommended for these so I put the same as SS\NR one. but why is this the reason for the issue? I mean, the switcher regulates very precisely without issues.

Quote
They show very little, the scale is 25ms and the waveforms are solid blocks of pixels indicating multiple cycles per pixel.  More like 10µs/div would be more interesting.

Tim

but doesn't it show the ripple period and its magnitude?



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Re: My PSU design ripple and noise with picture measurements
« Reply #45 on: September 01, 2021, 06:18:44 pm »
There are many periods and magnitudes of interest here...
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Re: My PSU design ripple and noise with picture measurements
« Reply #46 on: September 01, 2021, 07:49:47 pm »
Quote from: VEGETA
I didn't find a value recommended for these so I put the same as SS\NR one. but why is this the reason for the issue? I mean, the switcher regulates very precisely without issues.
"NP" near that cap means "do not place".
 

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Re: My PSU design ripple and noise with picture measurements
« Reply #47 on: September 07, 2021, 05:12:02 pm »
I am now re-making the board, I have attached the current schematic. I have added one common-mode choke to help attenuate the common-mode ripple if it exist. all 22uF caps are 1206 package instead of 0805.

I have started doing the PCB, right now I put full ground pour (solid, no thermal reliefs) and also top all solid ground plain except of course the traces. Each GND pad (filter caps, etc..)  has a very close via to ground plane.

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Re: My PSU design ripple and noise with picture measurements
« Reply #48 on: September 09, 2021, 06:44:37 pm »
I removed 1 22uF from each switchers to allow maximum of 200uF total capacitance.

Should I add 1uF before and after the common-mode choke?

right now this is the CMC I choose: https://www.lcsc.com/product-detail/Common-Mode-Filters_Murata-Electronics-DLW5BTM501SQ2L_C91597.html

relatively cheap murata from LCSC. I could go for cheaper stuff as well if they won't make a difference.

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Re: My PSU design ripple and noise with picture measurements
« Reply #49 on: September 09, 2021, 07:45:57 pm »
I have done the new layout based on last schematic. Please see it in attachments.

I put bottom layer full ground pour + top layer full ground pour except for the traces and vias. Also in top plane there is a small +12v pour near top right as you can see.

Nearly every cap GND pin has a ground via nearby very very close to it.

Please rate the design and give me your awesome feedback. I am willing to learn.

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Re: My PSU design ripple and noise with picture measurements
« Reply #50 on: September 09, 2021, 09:45:36 pm »
Can you show top copper with pours enabled?

You'll have a heck of a time soldering FL1, best check those pads.

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Re: My PSU design ripple and noise with picture measurements
« Reply #51 on: September 10, 2021, 10:33:05 am »
Can you show top copper with pours enabled?

You'll have a heck of a time soldering FL1, best check those pads.

Tim

they are in description.

it will be smt assembled not hand soldered.

do you think this will eliminate most or all cm noise?

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Re: My PSU design ripple and noise with picture measurements
« Reply #52 on: September 10, 2021, 01:14:24 pm »
Hmm, still can't figure it out, like why does the top copper not seem to pour over the bottom side traces?  They're both green, it's very ambiguous.

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Re: My PSU design ripple and noise with picture measurements
« Reply #53 on: September 10, 2021, 01:32:25 pm »
Hmm, still can't figure it out, like why does the top copper not seem to pour over the bottom side traces?  They're both green, it's very ambiguous.

Tim

What connector exactly?

I chose "solid" for copper pours, so all pads will blend in with the copper pour without thermal relief stuff. top side is red while bottom side is green.

I can make more photos if you want but kindly mention what exactly is the thing you want to see.

Also, will this solve the noise problem? the layout is good now? I am interested in those more.

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Re: My PSU design ripple and noise with picture measurements
« Reply #54 on: September 10, 2021, 02:01:44 pm »
I mean, like if I zoom in over here, the via seems to be completely surrounded by black.  Which is obviously absurd, why would it dead end?

Ohhhh, zooming in, and cranking the shit out of the brightness -- I can see what's going on.  The connecting trace has RGB 33,0,0 against a background of black 0,0,0 (original levels).  Your eyes must be much better than mine (or your monitor is, or, it's a whole lot worse..!), to actually be doing work like that?

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Re: My PSU design ripple and noise with picture measurements
« Reply #55 on: September 10, 2021, 02:02:50 pm »
Aha, amping up the red channel, and narrowing green a bit, gets something that looks a lot like old school Ultiboard. ;D

Why can't they use these as default settings though? :-//

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Re: My PSU design ripple and noise with picture measurements
« Reply #56 on: September 10, 2021, 02:17:16 pm »
So here's what I'd like to change:
- Move the traces to the blue paths.  This keeps ground solid under the regulators.
- Add vias where shown (blue circles).  This keeps top and bottom ground solid, stitching around traces.

Note that the inductor is not a high-current switching path, it's fine to run traces under there, within reason.  No problem from cutting the ground (i.e. the negative space created by pouring around a trace).  And this trace isn't sensitive to noise.

- Remove a couple caps (blue X's) and add a series inductor (purple).  This filters the 12V passthru/out.

All the filters are clustered around the bottom so the output connector should be nice and quiet.  The input connector is across the board so can pick up some switching noise, but at least the switching currents should be tightly contained, and are surrounded by lots of ground copper, keeping the voltage drop small.  And there's a CMC, which helps.

The overall number of capacitors is... rather obnoxious, but they don't hurt anything being there, they can always be depopulated on assembly.  Do check for compensation / stability (load step test).

The layout could be smaller, I suppose, for example if less space were taken up where 12V is routed around one regulator to the other; they could just be chained on the same trace, no problem.

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Re: My PSU design ripple and noise with picture measurements
« Reply #57 on: September 10, 2021, 03:10:34 pm »
Hello,

- I re-arranged those traces to make better grounding. I should not get feedback circuit under the noisy inductor, therefore I made those routes and re-routes. However, the other resistor is for power good function which doesn't care about noise but still managed to get it without going under the L.

- I didn't remove the 12v filter caps since I don't know the inductor value and therefore I could use 4.7uH which I used here. Plus I already put 4.7uH one as seen in schematic and layout (upper right). Do you mean I remove 22uF+47uF caps and put a 4.7uH instead just for output connector? since they won't be feeding the switchers.

- added more vias in different places.

number of output caps for each switcher stages are correct. I need total capacitance to be less than 200uF, here it is about 201uF or so... 1206 package is good for that despite they are putting 0805 in datasheets but that is mainly because they were interested in showing how this part actually reduces space. I have enough space therefore I can put such caps. They only recommended ceramic caps but I added an electrolytic 47u at the end.

It is possible to eliminate all 47uF elec. caps and just use 22uF ceramics since 1206 is kinda good with 3.3v and 5v. but 47u ensures more capacitance rather than get reduced by dc bias. plus, 12v is very harsh on ceramics due to dc bias.

from this and your opinion, how much noise\ripple can we get as a total figure? I really want it to be so low even if it is not fully needed to be so. perfection is always desired xD. Previous comments suggested that CMC is the key to reduce all this which is why I added it + the layout note about vias. I hope now it is done.

problem is I can't order this again due to high cost of assembly for mere 5 boards. JLCPCB doesn't have all the parts either, the TI switcher is impossible to hand solder! I am trying to have a solution which ensures very little cost to try at least 1 board fully assembled.

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Re: My PSU design ripple and noise with picture measurements
« Reply #58 on: September 10, 2021, 09:18:05 pm »
Yes, 4.7uH is fine.  You're not filtering the output from the input, you're filtering it from the switchers, which throw quite a lot of noise upstream.  It would likely be fine also to bypass it all, loop the raw input (after the CMC) around the side, down to the connector.

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Re: My PSU design ripple and noise with picture measurements
« Reply #59 on: September 10, 2021, 10:19:34 pm »
Quote
It would likely be fine also to bypass it all, loop the raw input (after the CMC) around the side, down to the connector.

meaning what exactly? putting ceramic caps around CMC?

I will put 4.7uH instead of those 2 caps next.

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Re: My PSU design ripple and noise with picture measurements
« Reply #60 on: September 10, 2021, 11:00:55 pm »
Bypass in the plain meaning, run the trace around the right edge, ignoring the internal 12V pour.

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Re: My PSU design ripple and noise with picture measurements
« Reply #61 on: September 11, 2021, 11:45:23 am »
Bypass in the plain meaning, run the trace around the right edge, ignoring the internal 12V pour.

Tim

you mean give it a separate path? this way it won't benefit from the huge 1000uF capacitor.

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Re: My PSU design ripple and noise with picture measurements
« Reply #62 on: September 11, 2021, 03:01:11 pm »
Who cares, don't need it anyway. Or put it on the other side of the 4.7uH.

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Re: My PSU design ripple and noise with picture measurements
« Reply #63 on: September 12, 2021, 06:06:58 pm »
Hello,

I have done it.

- re-arranged 12v stuff.
- added another 4.7uH inductor, now has 2 separate paths of 12v... one for output connector, one for switchers. Both stages supplied by 1000uF+47uF capacitors.
- each 12v stage has 22uF ceramic + 47uF elec. cap.
- layout is done where the 2 inductors are on the side.

is it good now? does it need anything else?

what noise\ripple expected now?

regards!

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Re: My PSU design ripple and noise with picture measurements
« Reply #64 on: September 13, 2021, 03:49:47 am »
Nice!

Hm, I would add one via:

That should do it.

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Re: My PSU design ripple and noise with picture measurements
« Reply #65 on: September 13, 2021, 05:24:25 am »
Nice?! you should say "marvelous" hhhhh xD

I will add that via today when I get back.

First time for me to know that adding vias like this is vital in PCB design. Also, that doing ground pour on both layers is the best way to go. However, in 4 layers stack, I guess I should have signal-gnd-gnd-signal stack right? since the 3rd layer can be a power layer but sometimes I would have multiple power rails which makes it difficult to put them all on one power plain, therefore making it gnd is better right? I could just route power on signal layers.

I understand that vias are short path to gnd which makes it easy for current to go to ground instead of travelling long distance, therefore noise will be significantly reduced overall. is that correct?

what is more to learn about this? what more improvement I can do? is the CMC part suitable and how to choose a suitable one?

most importantly, do you think I can achieve < 1mV total noise\ripple this way? maybe at least < 5mV p-p? how much exactly?

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Re: My PSU design ripple and noise with picture measurements
« Reply #66 on: September 13, 2021, 06:18:42 am »
Oh, one more thing but it's unrelated to electrical performance per se.  With all that copper, and via stitching, and direct-pour pads, you may find soldering is quite difficult.  Especially on those undersized pads for the CMC.  Basically the whole board needs to reach soldering temp before anything will melt.  And the direct-pour pads have extra surface tension that tends to lift components, leading to tombstoning, particularly when the other pad just has one or two traces leading out of it.  (Tombstoning isn't much of a problem for 0805 and larger, but is a concern for smaller chips.)  If nothing else, you'll have a hell of a time doing any rework with a soldering iron; hope you have a hot air machine.

2-4 spokes (thermal relief) drops just enough thermal resistance to make soldering a little easier, while having essentially no electrical impact, and for thermal dissipation purposes (at regular component-self-heating power densities) has little effect as well.  (That is, because soldering is done with more heat, the temp drop is higher, so the spokes are helpful there, while also being mostly inconsequential in operation.)

5mV is probably in the right ballpark.  I'd have to do some calculations to give a better guess.

Note that we still have not resolved whether your power adapter in the first place is the source of noise, nor of what the spectrum looks like (just a forest of spikes, modulated at 50Hz).  If it is the adapter, the CMC will at least help a bit, but you may still not observe the noise floor of the board itself, if this is the case.

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Re: My PSU design ripple and noise with picture measurements
« Reply #67 on: September 13, 2021, 06:30:38 am »
Oh, one more thing but it's unrelated to electrical performance per se.  With all that copper, and via stitching, and direct-pour pads, you may find soldering is quite difficult.  Especially on those undersized pads for the CMC.  Basically the whole board needs to reach soldering temp before anything will melt.  And the direct-pour pads have extra surface tension that tends to lift components, leading to tombstoning, particularly when the other pad just has one or two traces leading out of it.  (Tombstoning isn't much of a problem for 0805 and larger, but is a concern for smaller chips.)  If nothing else, you'll have a hell of a time doing any rework with a soldering iron; hope you have a hot air machine.

2-4 spokes (thermal relief) drops just enough thermal resistance to make soldering a little easier, while having essentially no electrical impact, and for thermal dissipation purposes (at regular component-self-heating power densities) has little effect as well.  (That is, because soldering is done with more heat, the temp drop is higher, so the spokes are helpful there, while also being mostly inconsequential in operation.)

5mV is probably in the right ballpark.  I'd have to do some calculations to give a better guess.

Note that we still have not resolved whether your power adapter in the first place is the source of noise, nor of what the spectrum looks like (just a forest of spikes, modulated at 50Hz).  If it is the adapter, the CMC will at least help a bit, but you may still not observe the noise floor of the board itself, if this is the case.

Tim

You mean choose "thermal relief" in Kicad instead of "solid" for ground pours? I can also make CMC pads bigger.

I won't be doing any rework stuff anyway, but adding thermal reliefs seems reasonable enough.

I hope I can get below 5mV if possible, how can you calculate that now?

there is nothing else besides the power adapter anyway. I used a reasonably-good one, I have worse. users might have better or worse too. the forest of spikes at 50 hz seems not good to me since this is not the switching frequency of the power adapter. therefore, we concluded here in this thread that it is CM noise. I think you can still see the ripple waves caused by the power adapter in the pictures.

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Re: My PSU design ripple and noise with picture measurements
« Reply #68 on: September 13, 2021, 08:08:49 am »
Yes, thermal relief.

Oh, and keep vias direct, thermals there just take up space.

Calculations require building a model, which will take several hours to do; I'm guessing you don't have the budget for me to do that, but if you like, references can be found for using simulators, and building EMI equivalent networks.  Which, without starting knowledge, it will take some, probably weeks to get up to speed -- well worth it if you're planning on making more supplies and stuff though.  Well... weeks, more like months including background material like how to setup and measure networks, RF port theory, CM/DM etc...

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Re: My PSU design ripple and noise with picture measurements
« Reply #69 on: September 13, 2021, 06:09:25 pm »
Done. I had to re-arrange stuff around switchers when making thermal reliefs.

I may increase the pad sizes of CMC if it is necessary.

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Re: My PSU design ripple and noise with picture measurements
« Reply #70 on: September 14, 2021, 04:48:07 am »
You have 1 trace which may be damaged by the mounting screw and the same thin trace right at the edge of the PCB. see photo for fix...
 

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Re: My PSU design ripple and noise with picture measurements
« Reply #71 on: September 14, 2021, 04:57:01 pm »
You have 1 trace which may be damaged by the mounting screw and the same thin trace right at the edge of the PCB. see photo for fix...

I fixed it, plus added some vias under inductors.

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Re: My PSU design ripple and noise with picture measurements
« Reply #72 on: September 14, 2021, 06:42:31 pm »
The reliefs seem pretty large, just 7 to 10 mils is enough expansion / clearance.  And similar for spoke/web width.

Which, huh, a few look super thick, like the uh, whatever the row of capacitors is above the middle regulator, I can't read the silk from here.  Looks like there's fat ass traces hidden by the polygon or something?  If those are required for connectivity / pouring, I'd shrink them, and align them with the spokes so you aren't creating extra or thickened ones.

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Re: My PSU design ripple and noise with picture measurements
« Reply #73 on: September 14, 2021, 08:42:19 pm »
The reliefs seem pretty large, just 7 to 10 mils is enough expansion / clearance.  And similar for spoke/web width.

Which, huh, a few look super thick, like the uh, whatever the row of capacitors is above the middle regulator, I can't read the silk from here.  Looks like there's fat ass traces hidden by the polygon or something?  If those are required for connectivity / pouring, I'd shrink them, and align them with the spokes so you aren't creating extra or thickened ones.

Tim

kindly check attached images. first one is for ground pour settings so you can see and advise which ones to change, the 2nd one is for showing the traces (blue arrow, red arrow, black arrow) to see which ones you mean.

if you mean blue arrow, this trace size is 2 mm which is the biggest since it is the main power input for the regulators as you can see... came from 12v rail. Should I shrink it a bit, to be 1? since there was nothing around it I thought of making it big.

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Re: My PSU design ripple and noise with picture measurements
« Reply #74 on: September 15, 2021, 09:20:27 am »
Yes the traces are too fat in places, they can be necked down locally, or for just an ampere or two they don't need to be very wide at all, 0.5 to 1mm.  And you can get 2oz copper for extra handling.

Yeah thermal relief and clearance, 0.254 mm will do.

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Re: My PSU design ripple and noise with picture measurements
« Reply #75 on: September 15, 2021, 07:04:24 pm »
Yes the traces are too fat in places, they can be necked down locally, or for just an ampere or two they don't need to be very wide at all, 0.5 to 1mm.  And you can get 2oz copper for extra handling.

Yeah thermal relief and clearance, 0.254 mm will do.

Tim

done.

- I have adjusted it to 0.254mm.
- I removed all GND traces under the vias which connected caps together, now only thermal reliefs are there.


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Re: My PSU design ripple and noise with picture measurements
« Reply #76 on: September 15, 2021, 10:49:02 pm »
Via 'A' may cook/fail if port 'B' draws above 250ma at 5v.  (I do not know drill size, so I'm uncertain.)
You may move that entire trace to the bottom layer, no need for a via.
 

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Re: My PSU design ripple and noise with picture measurements
« Reply #77 on: September 15, 2021, 11:22:53 pm »
done.

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Re: My PSU design ripple and noise with picture measurements
« Reply #78 on: September 21, 2021, 07:10:46 am »
Hello.

I skimmed over this thread since I was doing a buck PSU design myself recently and I have some remarks. One thing I noticed about your design is that you're running copper traces underneath or very close some inductors. For example, L2 and L3 seem to have a trace or two going back to the IC. Several papers on buck design that I've read advise against this practice because the inductors will introduce noise in whatever lies beneath and around them. The TPS6291x datasheet shows the two pins should be connected directly to an inductor, so I'm not sure, if that's going to be a problem or not. The buck feedback traces should also be routed away from inductors - you're running one such trace very close to L3.

See this document for example:
https://fscdn.rohm.com/en/products/databook/applinote/ic/power/switching_regulator/converter_pcb_layout_appli-e.pdf

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Re: My PSU design ripple and noise with picture measurements
« Reply #79 on: September 21, 2021, 02:45:18 pm »
I don't worry too much about trace proximity to inductors.  First it depends on shielded vs. open: if the latter, give more weight to the consideration.  Also, while you can't really figure it at design time, you can at least measure it in the prototype: just hold a loop nearby, approximately where the trace would be, and measure the induced voltage.  Intuitively, even for unshielded inductors, it can't be more than a N:1 fraction of the switching waveform, and falls quickly with distance.  Most inductors have a fair number of turns (for something like in this thread, say 10-20t; but it does go down to 1-3t in high current, high power inductors) so that's on your side.

For my part, I prefer putting pours around the inductors rather than thin connecting traces, simply to increase the power dissipation of the component.  Some heat may be sunk out of the regulator by the same means.  (Other likely routes are GND and VIN, one of which (GND most of all) is likely to be substrate and therefore thermally important.)

And with inner planes, proximity on opposite sides is irrelevant: even 0.5 oz copper planes are adequate to block 100kHz+. :-+

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Re: My PSU design ripple and noise with picture measurements
« Reply #80 on: September 22, 2021, 09:19:40 am »
I don't worry too much about trace proximity to inductors.  First it depends on shielded vs. open: if the latter, give more weight to the consideration.  Also, while you can't really figure it at design time, you can at least measure it in the prototype: just hold a loop nearby, approximately where the trace would be, and measure the induced voltage.  Intuitively, even for unshielded inductors, it can't be more than a N:1 fraction of the switching waveform, and falls quickly with distance.  Most inductors have a fair number of turns (for something like in this thread, say 10-20t; but it does go down to 1-3t in high current, high power inductors) so that's on your side.
I actually saw a masters thesis presentation earlier this year where coupling from a shielded inductor was actually causing significant EMI issues and change in behaviour of a buck converter eval board. Despite multiple other theories, the cause was tracked down to be coupling into a nearby voltage sensing pin. Quite the journey to track down and 100% confirm the root cause.
https://www.psma.com/sites/default/files/uploads/files/Impact_of_Power_Inductor_on_EMI_Performance_of_DCDC_Converters_Ammad_Javed_Ernst_Abbe_University_of_Applied_Science_Jena.pdf
« Last Edit: September 22, 2021, 09:23:23 am by sandalcandal »
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Re: My PSU design ripple and noise with picture measurements
« Reply #81 on: September 22, 2021, 12:27:53 pm »
I actually had the feedback pin from another path away from inductor, but got the suggestion here to route it this way near the inductor due to making a split in ground plain. should I get it back? maybe it is safer under the switcher than near L.

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Re: My PSU design ripple and noise with picture measurements
« Reply #82 on: September 22, 2021, 02:56:28 pm »
I don't worry too much about trace proximity to inductors.  First it depends on shielded vs. open: if the latter, give more weight to the consideration.  Also, while you can't really figure it at design time, you can at least measure it in the prototype: just hold a loop nearby, approximately where the trace would be, and measure the induced voltage.  Intuitively, even for unshielded inductors, it can't be more than a N:1 fraction of the switching waveform, and falls quickly with distance.  Most inductors have a fair number of turns (for something like in this thread, say 10-20t; but it does go down to 1-3t in high current, high power inductors) so that's on your side.
I actually saw a masters thesis presentation earlier this year where coupling from a shielded inductor was actually causing significant EMI issues and change in behaviour of a buck converter eval board. Despite multiple other theories, the cause was tracked down to be coupling into a nearby voltage sensing pin. Quite the journey to track down and 100% confirm the root cause.
https://www.psma.com/sites/default/files/uploads/files/Impact_of_Power_Inductor_on_EMI_Performance_of_DCDC_Converters_Ammad_Javed_Ernst_Abbe_University_of_Applied_Science_Jena.pdf

Hah, neat. Their fault for cramming the pin so tight I suppose, and also putting more than just an error amp on it (who knows what's in that "Direct Control and Compensation" box).  Note the problem would've been lessened if they had simply poured ground around the inductor (preferably with stitching)!

Irony being, the "problem" is advantageous, at least at the particular conditions measured; free spread-spectrum broadens and lessens the peaks.  What's disadvantageous is it's dependent, going away at higher input voltage evidently.

Tim
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Re: My PSU design ripple and noise with picture measurements
« Reply #83 on: October 05, 2021, 05:09:27 pm »
I have re-allocated the 3.3v feedback from being near the inductor to being from under the regulator... the only place available.

I also added more ground stitching vias on top near connectors, that area had 0 stitching vias.

I also made the pads of CMC bigger, now 1mmx1mm instead of 0.55mm or so.

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Re: My PSU design ripple and noise with picture measurements
« Reply #84 on: October 05, 2021, 06:45:13 pm »
EDITS:

1- downloaded and used the correct CMC footprint, it is DLW5BTM501SQ2L which is available cheaply on LCSC.
2- added more vias under caps and inductors.
3- added 3D models for all stuff to look fancy.
4- CMC has weird pads shape, which kicad doesn't add thermal reliefs by default. thus I added them manually to the best I could. please check


to do list:

- silkscreen stuff like component tags and so on.

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Re: My PSU design ripple and noise with picture measurements
« Reply #85 on: October 13, 2021, 09:58:59 pm »
what do you guys think now? I still have to clean up the silkscreen stuff.

I am interested in the final ripple and noise p-p figure, what to expect here?

plus, do you know a pcb house that can do only 1 or 2 assembled boards cheaply?

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Re: My PSU design ripple and noise with picture measurements
« Reply #86 on: October 14, 2021, 06:00:45 am »
Looks good.

If you if you want to go through the trouble and you have the parts, you can setup your own small SMD lab with a flat iron and arduino board, thermo couple and solid state relay.  Handy allowing you to make small PCB anytime:



I still prefer to use a stencil and old credit-card to apply the solder paste.  Using a stencil with the iron can get you to the edge of what will look like a professional SMD assembly job.
 

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Re: My PSU design ripple and noise with picture measurements
« Reply #87 on: October 14, 2021, 10:40:33 am »
I cannot do such setup right now unfortunately. Plus, some of these items are very very small (2mmx2mm for switchers). I hope there is a company which has small setup fees or so.

Do you have anything else I can do or add to make the design better?

Can we get < 5mV p-p total noise\ripple figure? I hope so.

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Re: My PSU design ripple and noise with picture measurements
« Reply #88 on: October 14, 2021, 12:39:02 pm »
Unfortunately, without PCB and a measuring scope, there isn't much that you can play with other than try to match the IC manufacturers recommendations.  If your inductors are a good match for the ones in the TI data sheet, you should get a clean output.  It is the question if your new source power-supply choke is big enough to isolate switcher noise from that 12v supply going throughout your system.  The other problem is that this noise can be down in the low KHz region.  Your PCB may be clean, but noise looping though even the ground of your source 12v supply can create a problem in the dreamcast where using a battery or linear 12v DC supply will be completely isolated from your AC wall outlet in a way no cheap Aliexpress 12v AC adapter switcher would be.  That is unless you make sure such a 12v switcher came from a reputable design.

(Youtube channel DiodesGoneWild -> https://www.youtube.be/channel/UCQak2_fXZ_9yXI5vB_Kd54g tears apart many of these switchers, he opens and unwinds the transformers themselves, and except for top name brands and an occasional fluke, most of them are garbage and fail on many levels.)

As for the switcher being 2x2mm.  Yes that is a headache, though when ordering PCBs with a SMT stencil, the paste application is easy.  Especially on small PCBs.  And when placing a device with tweezers, you do need to get it close, but not perfect as the device centers itself as the solder paste melts.

I've seen youtube videos of those using a frying pan with sand to spread the heat evenly before it reaches the PCB, but, the iron has a thermocouple right on its surface with precise temp control so nothing will get burnt.

Having mounting hardware means if you make a mistake or blow the component, or need to change a component, you can remove the part, clean it, and try again.  Though, I cannot blame you about wanting to have someone else already equipped and experienced to do it.
 

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Re: My PSU design ripple and noise with picture measurements
« Reply #89 on: October 14, 2021, 01:26:34 pm »
Just in case you want in the future:

http://electronoobs.com/eng_arduino_tut155.php

Aduino base hotplate with source code.
He used the stencil method of applying solder paste.
His resulting PCB looks better than some of the Aliexpress junk pre-made PCBs I have seen in the past.
 

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Re: My PSU design ripple and noise with picture measurements
« Reply #90 on: October 14, 2021, 04:05:41 pm »
Right now I am searching for cheap oscilloscopes. Here in Jordan we have picoscope 2204A but it is out of stock, and Hantek 6022be which doesn't have ac coupling and seem a bit bad.

I am thinking of asking here in the forum if anyone willing to giveaway or sell digital scopes at very cheap price so that it doesn't cost a lot in total. Best Amazon deal was this: https://www.amazon.com/Oscilloscope-Channels-Bandwidth-Portable-SDS1102X/dp/B089GG14BP/

for 230$ including shipping + 0$ import fees which I kinda doubt.

EDIT: I found this isolated one for 145$ total including shipping and import fees: https://www.amazon.com/OWON-VDS1022I-channels-Digital-Oscilloscope/dp/B07CNP2CJY/

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Re: My PSU design ripple and noise with picture measurements
« Reply #91 on: October 14, 2021, 06:54:28 pm »
I have arranged the silkscreen stuff properly now. Currently doing the BOM.

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Re: My PSU design ripple and noise with picture measurements
« Reply #92 on: October 27, 2021, 06:16:44 am »
I ordered Owon VDS-1022I USB scope, will arrive next week or so.

I am contacting my PCB assembled to make only one assembled board for testing purposes, this time I hope I get it correct. I hope noise and ripple are < 5 mv p-p total.

do you think I can achieve such a low level?
is there any modification to do before sending the gerbers?

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Re: My PSU design ripple and noise with picture measurements
« Reply #93 on: October 27, 2021, 06:52:15 am »
The 5mv will be difficult to measure as it will be within the noise range of the scope input.
And you may be reading noise just through the probe's GND clip or even local AM radio broadcasts.

Using the scopes input filters and running the probe in x1 mode will help here.

Also, remember that your goal is this low noise level when actually loaded by the Dreamcast, playing a CPU intensive game.  You should do fairly well.  I can only imagine needing to add a huge electrolytic cap on the 3.3v rail-gnd to help if the Dreamcast current load modulates like hell.
 

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Re: My PSU design ripple and noise with picture measurements
« Reply #94 on: October 27, 2021, 03:32:50 pm »
The 5mv will be difficult to measure as it will be within the noise range of the scope input.
And you may be reading noise just through the probe's GND clip or even local AM radio broadcasts.

Using the scopes input filters and running the probe in x1 mode will help here.

Also, remember that your goal is this low noise level when actually loaded by the Dreamcast, playing a CPU intensive game.  You should do fairly well.  I can only imagine needing to add a huge electrolytic cap on the 3.3v rail-gnd to help if the Dreamcast current load modulates like hell.

well, adding another big cap will be bad since it will exceed the maximum capacitance allowed by the switcher. it strictly advised to stick to it. I am at the top of it now. I am doing 201 uF instead of 200uF maximum... most of them are 22uF 1206 caps which will dip a bit to allow < 200uF effective capacitance. this is the total before and  after ferrite bead exactly as datasheet wants.

I previously used 0805 caps but now 1206.

AllPCB are doing free assembly these days so I will definitely use it.

The scope sensitivity is 5mV/Div, so even at 10 mv setting I can see the 5mv i guess. plus, this time common-mode noise should be gone or hugely eliminated which is always a plus.

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Re: My PSU design ripple and noise with picture measurements
« Reply #95 on: October 27, 2021, 04:45:20 pm »
It is good to have an oscilloscope because id is a universal device. And it definitely will help to fight with a ripple of any switcher. But be ready that it can't help much if you are interested in low-noise measurements (sub-millivolt).
 

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Re: My PSU design ripple and noise with picture measurements
« Reply #96 on: October 27, 2021, 05:01:05 pm »
It is good to have an oscilloscope because id is a universal device. And it definitely will help to fight with a ripple of any switcher. But be ready that it can't help much if you are interested in low-noise measurements (sub-millivolt).

sub-millivolt? well, if I can get to 1 mv I consider that fantastic, this project is targeting about 5 mV which is in the range of the scope which people report it is clean in terms of inherit noise.

what is your recommendation then?

right now at this stage VDS-1022I is the best choice for me.


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Re: My PSU design ripple and noise with picture measurements
« Reply #97 on: October 27, 2021, 05:17:12 pm »
well, adding another big cap will be bad since it will exceed the maximum capacitance allowed by the switcher. it strictly advised to stick to it. I am at the top of it now.
Yes, right at the switcher, the low impedance direct connection in the feedback path and GND.
But remember, in your Dreamcast, you have a ton of caps from VCC to GND throughout the PCB.  Your total is probably exceeding that 200uf limit by a few fold.

Just counting the electrolytics and tantalums in a photo of the dreamcast motherboard I see:
10+10+10+10+22+22+4.7+47+220+100+47+100+47+100+150+47+100=1046.7uf
Divide that by ~2 so you have half on 3.3v and half on 5v.
That's another 500uf not counting the sum of the tiny stuff.

This should not be a problem as you have a enough of a series resistance between your power supply PCB and the dreamcast itself in the power cables alone.

Yes, if you place a 2200uf cap on your PCB right where your other caps are on it, the switchers may oscillate and their mosfets and your inductors may get a huge current spike at power-up since it will look like a short to GND for a small instant if those caps have a low ESR.  This gets worse with a nice huge 22000uf cap.
« Last Edit: October 27, 2021, 05:20:35 pm by BrianHG »
 

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Re: My PSU design ripple and noise with picture measurements
« Reply #98 on: October 27, 2021, 06:10:33 pm »
well, adding another big cap will be bad since it will exceed the maximum capacitance allowed by the switcher. it strictly advised to stick to it. I am at the top of it now.
Yes, right at the switcher, the low impedance direct connection in the feedback path and GND.
But remember, in your Dreamcast, you have a ton of caps from VCC to GND throughout the PCB.  Your total is probably exceeding that 200uf limit by a few fold.

Just counting the electrolytics and tantalums in a photo of the dreamcast motherboard I see:
10+10+10+10+22+22+4.7+47+220+100+47+100+47+100+150+47+100=1046.7uf
Divide that by ~2 so you have half on 3.3v and half on 5v.
That's another 500uf not counting the sum of the tiny stuff.

This should not be a problem as you have a enough of a series resistance between your power supply PCB and the dreamcast itself in the power cables alone.

Yes, if you place a 2200uf cap on your PCB right where your other caps are on it, the switchers may oscillate and their mosfets and your inductors may get a huge current spike at power-up since it will look like a short to GND for a small instant if those caps have a low ESR.  This gets worse with a nice huge 22000uf cap.

I guess the dreamcast board may have your suggested amount but it is not direct at the rail itself like my caps. they are spread in the board in many stages and ICs, after and before other stuff. So I guess they don't count as mine or nearly.

I have another PSU made by someone else which is kinda the best in market, it only has 100uF elec cap at the output of each stage.. just that, no ceramics no others. I tested playing on it for hours and hours different games but still didn't notice any degrade in performance. I have double that capacitance.

the PSU and dreamcast are connected directly using pins, no wiring at all.

I think I will go with this current design. I do have extra 220uF through-hole caps (and other values) in hand so I can also test adding one of them in case something like you suggested happened. My scope will arrive in 7-10 days or so but the PCBs will take more.

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Re: My PSU design ripple and noise with picture measurements
« Reply #99 on: October 28, 2021, 02:42:58 pm »
what is your recommendation then?
I use an oscilloscope plus AC true-RMS microvoltmeter with 5 MHz range to work with sub-mV levels (It is simple and quite cheap old Soviet В3-57 microvoltmeter).
If you are fine with "near-1mV" RMS noise lever then an average oscilloscope itself possibly should be fine.
« Last Edit: October 28, 2021, 02:45:06 pm by Vovk_Z »
 

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Re: My PSU design ripple and noise with picture measurements
« Reply #100 on: October 28, 2021, 02:52:16 pm »
I ordered Owon VDS-1022I USB scope, will arrive next week or so.
It is good that it has galvanically isolated power lines. So you wan't have an excessive induced common mode noise.
 

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Re: My PSU design ripple and noise with picture measurements
« Reply #101 on: October 28, 2021, 03:10:58 pm »
first time I know about microvoltmeter but it doesn't look like it draws like an oscilloscope but rather a value like multimeter.

I think there are reasonably cheap or affordable oscilloscopes which can do 500uV/Div but are they good enough?

VDS-1022I is isolated yes, which means no common-mode from source.

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Re: My PSU design ripple and noise with picture measurements
« Reply #102 on: November 21, 2021, 08:00:20 pm »
I've got OWON VDS1022I and the attached images are taken by it for 3.3v and GND of both my PSU and other PSU. Notice that my psu is the old version which I posted its measurements before... the new improved version with proper grounding + CMC + better filtering + bigger sized ceramic caps is going to start being manufactured in 2-3 weeks due to chip shortage. will need time to arrive though.

summery of pictures:

My PSU:

ground noise floor: about 14 mv P-P with some noise on top.
3.3v regulated rail: about 17-20 mV P-P ripple with nearly no noise on top, just ripple.

Other PSU:

ground noise floor: about 5 mV P-P ripple with more noise on top.
3.3v regulated rail: about 11~12 mV P-P ripple with a lot of noise (40~50 mV P-P) on top of it.

Please check the images and tell me what do you think?


Offline T3sl4co1l

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Re: My PSU design ripple and noise with picture measurements
« Reply #103 on: November 21, 2021, 10:38:53 pm »
What does the power supply and probing setup look like?

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Re: My PSU design ripple and noise with picture measurements
« Reply #104 on: November 21, 2021, 10:45:53 pm »
I have it in attachments... just regular scope probing directly at rail itself.

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Re: My PSU design ripple and noise with picture measurements
« Reply #105 on: November 22, 2021, 12:45:09 am »
What about the power supply?

The loop area of the probe, and it laying over the input cable besides, may be picking up much more than you wanted, even with the CMC at the input there.

Another way to tell is if the spikes drop in level when you put multiple turns of ferrite bead on the scope probe.

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Re: My PSU design ripple and noise with picture measurements
« Reply #106 on: November 22, 2021, 03:41:54 am »
     You need to use 2 channels on your scope in differential mode to get the authentic noise output of your PSP. 

     Here's how:  Channel 1 on your test VCC (right on your power supply's GND output) and Channel 2 on GND (right on your power supply's GND output).  Both scope probes should be calibrated and both channels should be set to the same voltage and same bandwidth options.  Then you need to select the scope's math function and select channel 1 'minus' channel 2.  The math result display, sometimes it's a new third trace on the display, will be the true voltage noise coming out of your power supply.  Just move the VCC probe to test both rails.

     To verify that you are setup properly, if you move either probe, tying VCC to GND, or vice-versa, (IE: Both probes on VCC or GND) the math output should read 0mv noise.  (Or, at least as close to 0mv as your scope's input and sampler can get.)

     Move your 2 probes connections to the Dreamcast's power input and you will get the true noise as the Dreamcast's input.

     Your 2 probe's GND clips should be connected together to a common GND point on your PCB or Dreamcast.
« Last Edit: November 22, 2021, 05:00:31 am by BrianHG »
 
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Re: My PSU design ripple and noise with picture measurements
« Reply #107 on: November 22, 2021, 07:30:43 am »
     You need to use 2 channels on your scope in differential mode to get the authentic noise output of your PSP. 

     Here's how:  Channel 1 on your test VCC (right on your power supply's GND output) and Channel 2 on GND (right on your power supply's GND output).  Both scope probes should be calibrated and both channels should be set to the same voltage and same bandwidth options.  Then you need to select the scope's math function and select channel 1 'minus' channel 2.  The math result display, sometimes it's a new third trace on the display, will be the true voltage noise coming out of your power supply.  Just move the VCC probe to test both rails.

     To verify that you are setup properly, if you move either probe, tying VCC to GND, or vice-versa, (IE: Both probes on VCC or GND) the math output should read 0mv noise.  (Or, at least as close to 0mv as your scope's input and sampler can get.)

     Move your 2 probes connections to the Dreamcast's power input and you will get the true noise as the Dreamcast's input.

     Your 2 probe's GND clips should be connected together to a common GND point on your PCB or Dreamcast.

I will do that today, I think this owon scope supports math functions for sure.

Quote
What about the power supply?

The loop area of the probe, and it laying over the input cable besides, may be picking up much more than you wanted, even with the CMC at the input there.

Another way to tell is if the spikes drop in level when you put multiple turns of ferrite bead on the scope probe.

Tim

power supply is external laptop-style power brick. it is connected directly via the connector at the white plastic part, then 2 wires (red and black) goes to dreamcast. i guess i could move the scope probes a bit off it but even at current setup i think they are away enough not to pick up anything major but will try tonight.

notice that this design doesn't have a CMC and also with the bad grounding we talked about above. new design will arrive in a month or so.


but besides all this, what do you think of waveforms of both PSUs? which one is better?

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Re: My PSU design ripple and noise with picture measurements
« Reply #108 on: November 22, 2021, 09:04:38 pm »
please check setup and results of differential probing in attachments.

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Re: My PSU design ripple and noise with picture measurements
« Reply #109 on: November 22, 2021, 09:25:07 pm »
The connection and math look correct.
2 tests to make sure everything is ok.

1. tie the 2 GND scope probes together and to a different GND point than the power connector.

2. Tie the both probe's tip to the same VCC.  In your scope capture, channel 1 and channel 2 should both show the same signal exactly, but, the math channel should be flat with no signal at all.  If the math still shows something then double check your scope settings, or re-orient the probes so that they approach your PCB from the other side.  EMI may be entering through the probe casing and probe coax.

If in case #2, your you see the math channel flat with no signal, then once you move one of the probes from VCC to GND, the output you see on the 'math' channel will be authentic power supply noise at the connector.
 

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Re: My PSU design ripple and noise with picture measurements
« Reply #110 on: November 22, 2021, 09:28:51 pm »
CORRECTION: Channel #2 looks delayed compared to channel #1.  This should not be.  The spikes in channel #2 should line up with the spikes in channel #1.  The 2 should cancel each other out in the math channel.

Is there some sort of setting in the scope which delays the sampling of channel #1 and #2?
Is the sampling set to be simultaneous between both channels?

Do you have a bandwidth limiter, IE 20Mhz bandwidth set on one channel but not set on the other?


Like what I said in my test #2 above, tying both channel inputs together should show you the exact same signal on both traces and the math output should reveal a flat 0 signal.


Is it possible that your scope may sample the entirety of channel 1, stop, then sample the entirety of channel 2 at a different time instead of simultaneously sampling both channels?  This would be bad and make the differential measurement setup fail.
« Last Edit: November 22, 2021, 09:42:27 pm by BrianHG »
 

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Re: My PSU design ripple and noise with picture measurements
« Reply #111 on: November 22, 2021, 09:40:57 pm »
I think it's just aliasing from the super zoomed out view.  Try more like 100ns/div, trigger on a spike.

And you can take a closer look at that, see what (if anything) in the circuit correlates with the spike rate, and ringing frequency.

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Re: My PSU design ripple and noise with picture measurements
« Reply #112 on: November 22, 2021, 09:49:29 pm »
Another snapshot showing the exact same 2.25us delay on Vegeta's PCB.
That is such a huge delay for a scope, maybe it is a bug on the Owon software/firmware.
I cant imagine it being a circuit design delay in the scope's electronics as 2.25us would require a huge amount of wiring.  But in software, we are talking about having a bad relative sample offset, or, one channel is going through a software filter and the other isn't.

The samples speed is set to 50msps.  Maybe is Vegeta turned up the sample speed to the high MHz, maybe he can bypass the bug, but you would still need to check.

Though, connecting probe #1&#2 to the same point with these settings doesn't produce 2 identical readings, we know something is wrong with the scope, most likely a software or firmware issue.

There should not be a 2.25us skew between channels.  Maybe Owon didn't test this specific setup.  I wonder is turning off the 'math' may fix the problem and align the spikes, or choosing a different timebase.  If so, it is clearly a programming bug in Owon's software.  Unless you are experienced, you have no clue how many bugs I've been running into in recent years compared to the days of the old-fashioned CROs with regards to component datasheets and modern test equipment which haven't been properly tested with all use case scenarios.
« Last Edit: November 22, 2021, 10:08:40 pm by BrianHG »
 

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Re: My PSU design ripple and noise with picture measurements
« Reply #113 on: November 22, 2021, 11:26:25 pm »
I think it's just aliasing from the super zoomed out view.  Try more like 100ns/div, trigger on a spike.

And you can take a closer look at that, see what (if anything) in the circuit correlates with the spike rate, and ringing frequency.

Tim
You could be right, but the timed pairs coming out which I pointed to.

He is running the scope at 50msps for 2 channels but the scope is capable of 1ghz with 1 channel, 500msps with 2 channels.  Vegeta needs to increase record length to get the full 500msps as the expense of the USB display refresh might slow down, but with much greater precision display.  Though, if doing this shifts the timing of the 2 samples from 2.25us to 0.225us, it shows there still is a fundamental bug in the scope's software and it needs to be fixed to get the true Channel 1 minus Channel 2 view.
 

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Re: My PSU design ripple and noise with picture measurements
« Reply #114 on: November 22, 2021, 11:37:52 pm »
Found the 'problem', see image: (It's in you scope settings...)

Error: You should not be triggering on both channels 1 and 2.  Only trigger on channel 1 exclusively, otherwise, channel 2 will randomly or find the next trigger event and re-align to a non-parallel position based on its waveform completely screwing up the whole purpose of the differential measurement.  (IE, the scope is waiting for a trigger on channel 1, then it waits again for the next trigger on channel 2.  You do not want that.  Channel 1 and 2 need to be aligned in parallel, so, you should only be triggering on 1 channel.)

This is assuming using 2 separate triggers on 2 channels simultaneously does the same thing as it would do on my Tektronix scope.  With this setup, my scope would generate the exact same error and doing this when attempting the same A-B 'math' differential common-mode measurement, the 2 channels are no longer aligned giving me a flawed result.  The math is being done on the sample data in the window with the relative alignment position you see, not like an old cathode ray tube analog scope where the input A-B function is done at the analog stage in the probe input amplifiers where such an alignment error could not be made.

Once again, if set correctly, my test#2 above, with Channel 1&2 on the same VCC should generate an identical signal on each trace while the 'math' channel should show dead flat 0.

The 50msps should also be able to be increased by using a longer record length as the Owon scope in use can do 1ghz, with a 10 million sample record.  Increasing this setting would generate a far greater refined scope shot and more accurate measurements even if you keep the horizontal zoom level at the current 5us/div.  (Assuming the Owon has enough ram, otherwise, the only way is to zoom in the time-base.)
« Last Edit: November 23, 2021, 02:21:01 am by BrianHG »
 

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Re: My PSU design ripple and noise with picture measurements
« Reply #115 on: November 23, 2021, 07:18:42 am »
So to sum up, I need to disable channel 2 triggering while keeping channel 1 triggering? so channel 2 can be active but take triggering from channel 1? I am new to using the scope so I would need some assistance. I will try that tonight when I return.

Also, you recommend changing sampling to just 50 instead of 500?

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Re: My PSU design ripple and noise with picture measurements
« Reply #116 on: November 23, 2021, 08:21:29 am »
So to sum up, I need to disable channel 2 triggering while keeping channel 1 triggering? so channel 2 can be active but take triggering from channel 1? I am new to using the scope so I would need some assistance. I will try that tonight when I return.

Also, you recommend changing sampling to just 50 instead of 500?
Point #1, you are correct.

Point #2, since I do not know about your scope, this speed might be a hardware limitation.  If so, zooming in on the horizontal time-base will improve the speed.  Or, you may be able to increase the sampling setting at the cost of the on-screen display refresh running slower.  This you will have to find out on your own.  500msps means the sampler is running at 500MHz instead of 50MHz, but, there will be 10x the data to send to your PC to display the same amount of width on the scope display.
« Last Edit: November 23, 2021, 08:23:11 am by BrianHG »
 

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Re: My PSU design ripple and noise with picture measurements
« Reply #117 on: November 23, 2021, 09:11:03 pm »
i did this, please see.

i couldn't modify sampling, it is auto

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Re: My PSU design ripple and noise with picture measurements
« Reply #118 on: November 23, 2021, 09:37:34 pm »
In this snapshot: both_channels_on_3.3v.PNG, if both channels were on 3.3v, how is it possible that channel 1 shows the ripple and channel 2 is flat?  Could you have disconnected your probe?  If both probes are on the same source signal with the same settings, they should show you the same image.

Also, because of the sampling frequency, you should set channel 1 & 2 bandwidth limiter to 20MHz.  The view will be cleaner and for this level of zoom, probably more accurate.

« Last Edit: November 23, 2021, 09:40:44 pm by BrianHG »
 

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Re: My PSU design ripple and noise with picture measurements
« Reply #119 on: November 24, 2021, 12:16:08 am »
In this snapshot: both_channels_on_3.3v.PNG, if both channels were on 3.3v, how is it possible that channel 1 shows the ripple and channel 2 is flat?  Could you have disconnected your probe?  If both probes are on the same source signal with the same settings, they should show you the same image.

Also, because of the sampling frequency, you should set channel 1 & 2 bandwidth limiter to 20MHz.  The view will be cleaner and for this level of zoom, probably more accurate.

I have re-taken the images right after I named them, so this picture is ch1 on 3.3 and ch2 is on gnd.

I have searched for limiting stuff but couldn't find, maybe I should search more, please tell me if you know the option. but what is your opinion on the waveforms regardless?

I have now modified the picture to have correct name.

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Re: My PSU design ripple and noise with picture measurements
« Reply #120 on: November 24, 2021, 12:59:10 am »
I don't see the both channels on VCC 3.3 screenshot.

You wont find the limiting stuff, your scope is already only 25MHz analog bandwidth anyways.
« Last Edit: November 24, 2021, 01:03:33 am by BrianHG »
 

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Re: My PSU design ripple and noise with picture measurements
« Reply #121 on: November 24, 2021, 07:09:53 am »
I don't see the both channels on VCC 3.3 screenshot.

You wont find the limiting stuff, your scope is already only 25MHz analog bandwidth anyways.

I can take this picture for you if you need to see it, but I remember it was like the grounds one.

I feel like it didn't really make the subtraction, or am I wrong? the resultant waveform seem nearly identical to 3.3v one, I don't feel there is a reduction based on ground signal. what do you think?

based on waveforms for both PSUs, what do you think of each?

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Re: My PSU design ripple and noise with picture measurements
« Reply #122 on: November 24, 2021, 07:19:38 am »
It shouldn't be like the GND snapshot.

Channel 1 should have the pulsing noise.
Channel 2 should have the same pulsing noise.
Channel M should be flat, assuming your setup is correct.

Your GND snapshot has 3 channels,  #1 & #2 & #M all flat.

We are verifying to see if your measurement scope setup and probes are all setup identically and properly.  1 mistake, and the result will not look as I described above.  1 mistake and what you see in the 'M' channel is useless for this type of measurement.
 

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Re: My PSU design ripple and noise with picture measurements
« Reply #123 on: November 24, 2021, 09:01:18 am »
It shouldn't be like the GND snapshot.

Channel 1 should have the pulsing noise.
Channel 2 should have the same pulsing noise.
Channel M should be flat, assuming your setup is correct.

Your GND snapshot has 3 channels,  #1 & #2 & #M all flat.

We are verifying to see if your measurement scope setup and probes are all setup identically and properly.  1 mistake, and the result will not look as I described above.  1 mistake and what you see in the 'M' channel is useless for this type of measurement.

yes this is what i meant by line grounds... ch1 and 2 are similar and the result is flat.

I will see tonight, will replicate the test again. but for now please assume it is correct. so, what is your opinion on this?

will proper grounding and separate paths for 12v + 1206 caps + ground stitching done on the newer version (still not arrived).. will this make it better by noticeable amount? at least better than other_PSU

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Re: My PSU design ripple and noise with picture measurements
« Reply #124 on: November 24, 2021, 09:26:07 am »
will proper grounding and separate paths for 12v + 1206 caps + ground stitching done on the newer version (still not arrived).. will this make it better by noticeable amount? at least better than other_PSU
I believe the other PSU is just operating at a much lower frequency, hence using larger inductors and larger caps makes the signal softer.

Yes, at higher frequencies, the choice of inductors and cap quality will play a part in the output ripple.

Your first measurements from 2 days ago show a leakage on both PSUs, a set of dual pulses at 50Hz.  This is usually a bleeding ground loop from the AC mains from your source supply and it Y1 cap and primary rectifier diodes.  It typically causes a faint buzz in the audio and hum-bar scrolling through the picture.  If this is part of the problem you are getting, no small switching supply can fix this as different measures are needed to get rid of this.  This would be an annoying AC mains looping frame ground problem I've seen with some 12v supply, perhaps like the one feeding your switcher when you have the output of the Dreamcast attached to another device like the scope GND clip, or your TV's video input.  If this was the actual problem, you would not see this with an analog power supply feeding the 12v input or using an isolator transformer on your AC mains feeding the 12v supply.  A proper differential measurement of the output on your switcher will determine if it is reacting to such a problem, but, we need to know the measurement you are making is true.

As for the 2MHz ring, yes, with a scope, we can sniff some of your PCB and find a solution.
 

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Re: My PSU design ripple and noise with picture measurements
« Reply #125 on: November 24, 2021, 10:11:57 am »
yes the other power supply uses lm2596 which has 150 khz switching frequency, with big inductor has "330" label on it, but output caps are just 100uF elec. caps per rail. it has solid ground plain though.

Mine runs about 2 MHz switching, therefore smaller inductors. I assume solution is already done on the newer version, perhaps check the previous replies to find it. we put CMC + one ground plain with lots of stitching + short loops for switchers + bigger ceramic caps + more input filteration + making 12v output using a separate path with separate filters than the 12v fed into the switchers. I think we all agreed back then that it would be good to solve all issues but we are waiting the PCBs which will take 4 weeks.

So lets discuss the benefit of choosing slow frequency vs fast frequency switching here... what could be the best to use? faster switchers seem more desired these days but what in terms of noise\ripple?

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Re: My PSU design ripple and noise with picture measurements
« Reply #126 on: November 24, 2021, 01:30:32 pm »
Best for what?  Ripple?  Non sequitur -- ripple can be made arbitrarily low, given adequate filtering and shielding.  It's the other constraints that limit performance: size and cost primarily, with efficiency, component selection, V/I range, etc. also being relevant.

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Re: My PSU design ripple and noise with picture measurements
« Reply #127 on: November 24, 2021, 01:44:36 pm »
Best for what?  Ripple?  Non sequitur -- ripple can be made arbitrarily low, given adequate filtering and shielding.  It's the other constraints that limit performance: size and cost primarily, with efficiency, component selection, V/I range, etc. also being relevant.

Tim

i mean for my application, 50x50mm board, low noise\ripple requirements as much as possible.

my switchers promised < 1 mV of total ripple and noise but the case in real life is not like this. we addressed this to be a grounding problem with what I explained in the previous post. so the new version of the circuit is on route.

down through that we landed on the idea that it is also common-mode noise, so CMC is added. I guess CMC can also help in regular noise suppression since it is a big L after all right?

however, low frequency stuff could have less worse ripple\noise if filtered through large L and C right?

I didn't address the PSRR of the switchers, which is a good value really. but the < 1mV is supposed to be assuming no ripple\noise on the input to begin with. but in my case and most cases, there are a ton of ripple\noise. So I needed to use more filters, bigger caps, better grounding to address this issue.

I am hyped about the new design, hoping to be the last one.

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Re: My PSU design ripple and noise with picture measurements
« Reply #128 on: November 24, 2021, 08:30:29 pm »
this is both channels on 3.3v for my psu

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Re: My PSU design ripple and noise with picture measurements
« Reply #129 on: November 24, 2021, 09:37:04 pm »
Ok, you have proven that your scope can properly do a differential measurement.
Meaning if you place channel #1 on the VCC and #2 on the GND with this setup, the MATH channel will show your true noise at the output.

Also, looking at the current background noise in the MATH channel, your scope's approximate background noise level is ~15mv p-p.  It might be possible to turn on the scope's measurement stats for the MATH channel as well.

Now, your scope's timebase is 10ms/div and the waveform is approximately 2 divisions long.
IE: 1s/0.020 = 50Hz.  Is this correct?

If so, this interference is not your switcher oscillating, it's a leakage from your AC mains bleeding into/through your circuit.  Changing a tiny output cap or inductor on your PCB will not solve this problem.  (Those changes are to correct problems at the 2MHz switching speed which we cannot currently see.)  Now that your scope is properly setup, please do the differential measurement of the rail, with both probe GND clips tied together, then clipped to the dreamcast's GND through a series 100ohm-up to-1kohm resistor.  The purpose of this measurement is to verify that the route of this 50Hz interference isn't coming from a looping GND throughout your multiple AC main power supplies throughout your measuring scope's GND.  Verify that with the same time-base setting that your competitor's board doesn't bleed through the same 50Hz.

(You might as well test the 12v rail too.  This interference may be coming through there.)

If your video output is 50Hz, this may be CPU processing load once every V-sync.  To verify this, load a different game and this waveform's duty cycle should change or disappear.  If this is the case, then we need to look at the regulation feedback filter on your PCB and again, the same test is worth looking at on your competitor's PCB.  Also, this 50hz signal may not be on the 5v rail if it is due to CPU processing modulating current draw when rendering each frame.
« Last Edit: November 24, 2021, 10:41:02 pm by BrianHG »
 

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Re: My PSU design ripple and noise with picture measurements
« Reply #130 on: November 25, 2021, 11:34:11 am »
Quote
Ok, you have proven that your scope can properly do a differential measurement.
Meaning if you place channel #1 on the VCC and #2 on the GND with this setup, the MATH channel will show your true noise at the output.

this was the case in previous images. last image was just because I forgot to do it with the rest.

Quote
Also, looking at the current background noise in the MATH channel, your scope's approximate background noise level is ~15mv p-p.  It might be possible to turn on the scope's measurement stats for the MATH channel as well.

I didn't find it, but since all channels are the same vertical resolution (20mV/Div)... I just use ch1 measurement to measure all waveforms.

Quote
Now, your scope's timebase is 10ms/div and the waveform is approximately 2 divisions long.
IE: 1s/0.020 = 50Hz.  Is this correct?

I wasn't paying attention... perhaps the pictures above contain this info.


Quote
Now that your scope is properly setup, please do the differential measurement of the rail, with both probe GND clips tied together, then clipped to the dreamcast's GND through a series 100ohm-up to-1kohm resistor.

Will do it soon.

Quote
The purpose of this measurement is to verify that the route of this 50Hz interference isn't coming from a looping GND throughout your multiple AC main power supplies throughout your measuring scope's GND.  Verify that with the same time-base setting that your competitor's board doesn't bleed through the same 50Hz.

So i should do this measurement setup for both my psu and the other one?

ok but what to expect in both cases? I mean why the resistor?

Quote
If your video output is 50Hz, this may be CPU processing load once every V-sync.  To verify this, load a different game and this waveform's duty cycle should change or disappear.  If this is the case, then we need to look at the regulation feedback filter on your PCB and again, the same test is worth looking at on your competitor's PCB.  Also, this 50hz signal may not be on the 5v rail if it is due to CPU processing modulating current draw when rendering each frame.

this is interesting.

I cannot do it now but will find an SD Card to load games on it then use it since I have gdemu not a gd-drive.

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Re: My PSU design ripple and noise with picture measurements
« Reply #131 on: November 25, 2021, 05:24:55 pm »
Quote
Now, your scope's timebase is 10ms/div and the waveform is approximately 2 divisions long.
IE: 1s/0.020 = 50Hz.  Is this correct?

I wasn't paying attention... perhaps the pictures above contain this info.
Yes they do.
Quote

Quote
Now that your scope is properly setup, please do the differential measurement of the rail, with both probe GND clips tied together, then clipped to the dreamcast's GND through a series 100ohm-up to-1kohm resistor.

Will do it soon.
Ok.
Quote

Quote
The purpose of this measurement is to verify that the route of this 50Hz interference isn't coming from a looping GND throughout your multiple AC main power supplies throughout your measuring scope's GND.  Verify that with the same time-base setting that your competitor's board doesn't bleed through the same 50Hz.

So i should do this measurement setup for both my psu and the other one?

ok but what to expect in both cases? I mean why the resistor?
The resistor separates the scope's GND from your PSU GND just in case the 50Hz ripple is running throughout the GND.  It may also be useful to check if with the Dreamcast disconnected from any TV if it is currently wired there.
Quote

Quote
If your video output is 50Hz, this may be CPU processing load once every V-sync.  To verify this, load a different game and this waveform's duty cycle should change or disappear.  If this is the case, then we need to look at the regulation feedback filter on your PCB and again, the same test is worth looking at on your competitor's PCB.  Also, this 50hz signal may not be on the 5v rail if it is due to CPU processing modulating current draw when rendering each frame.

this is interesting.

I cannot do it now but will find an SD Card to load games on it then use it since I have gdemu not a gd-drive.
Yes, if the Dreamcast is currently rendering a really simple scene, IE drawing 3 amps for part of a frame, then going down to 0.5 amps for the rest, this 50hz ripple we see would be within the regulator's transient load response and would probably only show on the 3.3v rail.  The other PSU you have may be doing the same thing, you just need to measure that supply with the same scope settings.

Typically, this type of problem would be solved with either a low esr bulk capacitor on the 3.3v output right at the PSU power connector, or, modification of the feedback filter for the regulator's 3.3v sense circuit, or use a heavy-duty over-current regulator which wont react to such a transient.  However, now with a scope capable of a differential measurement, you can now measure ripple on the feedback resistor network VS the output to trace the problem.
 

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Re: My PSU design ripple and noise with picture measurements
« Reply #132 on: November 25, 2021, 07:10:17 pm »
So to sum up, which test should I do for now without the game? which ones with the game? so I can do it.

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Re: My PSU design ripple and noise with picture measurements
« Reply #133 on: November 25, 2021, 09:06:07 pm »
You may skip the game for now if you like.  Just measure the 2 PSUs with the same settings on the scope.

If you are going to test a game:
Does the Dreamcast have a demo or power-up test mode?
Look for a game with just a still intro screen which stays on.
We just want to see if it changes the waveform you see now because a 50hz signal can be coming from the AC mains, or, just the right CPU intensity processing in a PAL vidoe system.
 

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Re: My PSU design ripple and noise with picture measurements
« Reply #134 on: November 25, 2021, 09:47:32 pm »
Also, if it's power sag or interference from your power source, have you considered it's your input power choke?
Did you try shorting it out?

Also, what about placing a 2200uf cap on the power output connector?  (When powered off of course, the powering on.)
What does your scope output look like with the probes on the cap?

In your scopeshots, I didn't see anything saying that the probe was set to 10x or 1x.  Do you have a 10x/1x setting on your probes?
« Last Edit: November 25, 2021, 09:49:06 pm by BrianHG »
 

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Re: My PSU design ripple and noise with picture measurements
« Reply #135 on: November 25, 2021, 10:12:33 pm »
Also, if it's power sag or interference from your power source, have you considered it's your input power choke?
Did you try shorting it out?

Also, what about placing a 2200uf cap on the power output connector?  (When powered off of course, the powering on.)
What does your scope output look like with the probes on the cap?

In your scopeshots, I didn't see anything saying that the probe was set to 10x or 1x.  Do you have a 10x/1x setting on your probes?

I got the probes to x1 to be able to measure beyond 50mV/div.

I don't have a CMC in this circuit, please remember that this is the old circuit... CMC and grounding solution is on new circuit which is on route.

you mean putting very big elec. cap on 12v input from the ac-dc power brick? since I cannot put that much capacitance on 3.3v or 5v output since switchers specify 200uF maximum capacitance as a must... I am about 20uF away from that on this board and about 200uF on new board.

so the tests i should do for now includes this resistor from DC ground to my scope ground leads for both PSUs right?

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Re: My PSU design ripple and noise with picture measurements
« Reply #136 on: November 26, 2021, 12:33:27 am »
Also, if it's power sag or interference from your power source, have you considered it's your input power choke?
Did you try shorting it out?

Also, what about placing a 2200uf cap on the power output connector?  (When powered off of course, the powering on.)
What does your scope output look like with the probes on the cap?

In your scopeshots, I didn't see anything saying that the probe was set to 10x or 1x.  Do you have a 10x/1x setting on your probes?

I got the probes to x1 to be able to measure beyond 50mV/div.

I don't have a CMC in this circuit, please remember that this is the old circuit... CMC and grounding solution is on new circuit which is on route.

you mean putting very big elec. cap on 12v input from the ac-dc power brick? since I cannot put that much capacitance on 3.3v or 5v output since switchers specify 200uF maximum capacitance as a must... I am about 20uF away from that on this board and about 200uF on new board.

so the tests i should do for now includes this resistor from DC ground to my scope ground leads for both PSUs right?

Yes on the resistor PSU tests.
The elect cap should be on the 3.3v.
Yes, I know you exceed the recommended switcher's rating.  If you are afraid of oscillation due to a lemon value of cap, going to 4700uf or 10000uf cap should be too high to allow the switcher to inject odd oscillations into the 3.3v rail.
 

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Re: My PSU design ripple and noise with picture measurements
« Reply #137 on: November 30, 2021, 07:32:24 pm »
Hello

done the resistor test for my psu, check it in pictures with names.

Here are some comments on pictures:

- odd behavior picture:

this happened after testing several caps to get results for other pics, such as 220uF, 1000uF, and 2200uF. then I noticed the waveform is flat with periodic bump as you see. I hooked up the video output and saw the picture completely messed up!! please see it in detail. it blinks each half a second or so while the colors are messed up a lot... slow functionality too like some delay until it registers a button move. I really regret doing the cap thing now since it ruined my dreamcast for reasons I don't know! messed up screen picture is in 2nd post.




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Re: My PSU design ripple and noise with picture measurements
« Reply #138 on: November 30, 2021, 07:33:15 pm »
here is the messed up screen.

any way to know the issue or fix it?

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Re: My PSU design ripple and noise with picture measurements
« Reply #139 on: November 30, 2021, 09:24:25 pm »
hello

after disassembling it and re-assembling it, it stopped turning on! it turns on for a brief moment then shuts off.. i measured about 86 ohms from 3.3v to gnd unlike 5v which is open load, so suspected something wrong.

checked many components which deals with 3.3v, left pins, etc.. but still 85 ohms... to make it worse I destroyed a sharp 07vz1h regulator! even after this regulator is out, still 85 ohms.

check pics: https://slow.pics/c/JOSrApga



EDIT: it now powers on completely with fan and so on, voltages are ok but there is no output picture. I measured voltages on caps and found the cap highlighted in picture to have 0v on its + side and about -0.5v on its negative side: https://slow.pics/c/PGsUaNuK

EDIT 2: that sharp regulator takes 3.3v and outputs 2v according to this schematic: https://archive.org/details/Dreamcast_Schematics_U
what is going on? could it be that that regulator supplies power to output video?

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Re: My PSU design ripple and noise with picture measurements
« Reply #140 on: November 30, 2021, 11:30:32 pm »
Yeah, it's a good idea not to plug in capacitors randomly to powered circuitry.

Toasted regulator?  Ah, seems likely the large capacitor effectively shorted out the main supply, reversing the regulator, with more current than it can handle.  Lucky it wasn't something much worse?  Or maybe that's just the first thing of notice...

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Re: My PSU design ripple and noise with picture measurements
« Reply #141 on: November 30, 2021, 11:45:56 pm »
Yeah, it's a good idea not to plug in capacitors randomly to powered circuitry.

Toasted regulator?  Ah, seems likely the large capacitor effectively shorted out the main supply, reversing the regulator, with more current than it can handle.  Lucky it wasn't something much worse?  Or maybe that's just the first thing of notice...

Tim

most of the times i shut the system off, then plugged the cap and turned it on. but yes did put caps while it was working, just not many times.

I still don't understand what went wrong till now. the regulator made by sharp wasn't bad or at least I didn't verify it. I went along the board trying to disconnect all 3.3v related regulators and destroyed it by being a super saiyan in a wrong time and place.

but even if without destroying it, the picture was distorted. but now it works and turns on but no picture at all... which makes me thing the video circuitry got the problem. don't know if it is the analog video or the gpu itself.

that cap is showing reversed voltage which is very weird. it needs more investigation but now I ordered a new dreamcast locally which I learned to be more careful.


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Re: My PSU design ripple and noise with picture measurements
« Reply #142 on: December 01, 2021, 03:59:18 am »
I so sorry to hear your dreamcast got damaged up.  Like 'T3sl4co1l' and what I wrote in my original post:

Also, what about placing a 2200uf cap on the power output connector?  (When powered off of course, the powering on.)

The cap had to be secure and not attached/detached while powered on as it may appear as a short, or, a voltage surge if the cap had a charge.

here is the messed up screen.

any way to know the issue or fix it?

It looks like a data bit in memory is stuck low.
This is odd because corrupt memory usually means the CPU wouldn't be able to do anything at all.
And yet your CPU is still working and executing code.

When you say it may be in the video output section, it is rare that this could be the video DAC, but not impossible.

Does anything else work?
Is there audio?

Were you able to replace the busted regulator?

Looking at the schematics, can you probe IC 401, with your probe in 10x mode for the high frequency, and check the data line inputs to see if any are stuck as well as the outputs?

Found cleaner scan of schematics here:  https://console5.com/wiki/Dreamcast
« Last Edit: December 01, 2021, 04:21:12 am by BrianHG »
 

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Re: My PSU design ripple and noise with picture measurements
« Reply #143 on: January 05, 2022, 04:04:55 pm »
Hello,

new boards have arrived, and looks like we nailed it perfectly this time!
 
I probed using differential probing of 2 channels then math function as done previously, also using the same 12v regulator. Now on a new dreamcast which is working fine. no game used though, and has its gd drive in place while the previous one used a clone gdemu.

Here are the details:

- org: original PSU from SEGA.
- mine: 2 pics, one measuring ripple only and one including noise spikes.
- competitor: 2 pics, one for ripple only and one including noise spikes. this one similar to the one used before.


Results:

original: about 65-70mV p-p ripple with no noise spikes. I kinda expected better.

mine: about 9mV p-p of ripple and about 31mV p-p noise spikes which are not a lot.

competitor: around 20mV p-p ripple and about 45mV p-p noise spikes.

please check the waveforms and tell me your opinion.


I conclude that CMC + grounding enhanced the design significantly, it is now more than 2 times better than best competitor. certainly more than good enough as a high quality product. Stock PSU still excels more at grounding as seems from the yellow noise or maybe that it doesn't use any high frequency switching (fly-back) plus its own CMC made it better to suppress noise, or more clearly it doesn't make noise.

Looking forward to your feedback!

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Re: My PSU design ripple and noise with picture measurements
« Reply #144 on: January 05, 2022, 05:54:53 pm »
Shrug, that's just output resistance.  Well within limits it seems.  What about the switching ripple, what's it look like around 1us/div?

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Re: My PSU design ripple and noise with picture measurements
« Reply #145 on: January 05, 2022, 06:52:46 pm »
Zoom into and trigger/capture the spikes.
They are too high frequency and being mucked up by the slow sampling rate and 10ms/div speed.

Your new supply seems immune to that 50hz buz in the signal.

For the high frequency spikes, if they are there in the differential when zoomed in on the time base, then they are authentic.
Because of their high frequency, strategically placed 1-10nf caps in the right place or strategically positioned ferrite bead should get rid of them.  Then you will be pretty much on par with an analog supply.

« Last Edit: January 05, 2022, 06:54:43 pm by BrianHG »
 

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Re: My PSU design ripple and noise with picture measurements
« Reply #146 on: January 05, 2022, 07:37:56 pm »
Shrug, that's just output resistance.  Well within limits it seems.  What about the switching ripple, what's it look like around 1us/div?

Tim

I don't understand what you mean by just output resistance.

I probed exactly like all previous times, literally the same. the psus are on the actual device and it is running. now gd-drive instead of gdemu. gonna try gdemu next time which will add a small load

Quote
Zoom into and trigger/capture the spikes.

aren't the spikes fully visible hear? or you want the trigger level to be on them so that normal signal is not triggering?

Quote
They are too high frequency and being mucked up by the slow sampling rate and 10ms/div speed.

I will try that next week (tonight is just this) but I think I changed to different time bases and saw nothing hidden or special. same method for other supplies as well.

Quote
Because of their high frequency, strategically placed 1-10nf caps in the right place or strategically positioned ferrite bead should get rid of them.

adding a small 10nf ceramic on each rail is doable but where? the space is limited, and I think I have some small through hole ceramic caps in this range available right now... so I could use them in this current circuit without building a new one. next pcb should be a small production batch not a test one.

Quote
Then you will be pretty much on par with an analog supply.

can you kindly explain?



so assuming this psu still the way it is here, is it good in your opinion? what specs should I write for it in its product page besides (high quality low noise PSU...)?

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Re: My PSU design ripple and noise with picture measurements
« Reply #147 on: January 05, 2022, 08:47:34 pm »

Quote
Zoom into and trigger/capture the spikes.

aren't the spikes fully visible hear? or you want the trigger level to be on them so that normal signal is not triggering?

They are 1 pixel wide.  What is their shape and frequency?
Spikes seem to exist on both the GND and VCC channels, and with 1 pixel wide spikes, maybe you are seeing a sample on one input channel and not the opposite one due to the sample being missed as it is 1 pixel wide.

As for analog power supply comparison, most switching supplies have a continuous ringing on their output when under load.  Since you are not zoomed in, I don't see this interference problem.  Though we still cannot also see perhaps an EMI coming out of your switcher.  Most likely, you will need to run your probe in 10x mode with the scope time-base set to the sub uS range to see anything there as your new supply operates in the 2MHz range and if switching noise is getting through the output filter, that signal will have edges up in the 500-200ns range.  An analog linear supply will not generate this type of noise.
 

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Re: My PSU design ripple and noise with picture measurements
« Reply #148 on: January 05, 2022, 09:07:37 pm »
I don't understand what you mean by just output resistance.

Measure load current.  I think you will find it's pulsing up and down at the vertical refresh rate.  (This will be a PAL or SECAM model, I expect?).  Thus, the voltage is changing in relation to load current: output resistance.

This has nothing to do with the converter's switching cycle, at some 100s of kHz.


Quote
aren't the spikes fully visible hear? or you want the trigger level to be on them so that normal signal is not triggering?

Beats me.  I don't know your scope.  Is it aliasing the spikes?  Are they really spikes?  Is it switching ripple?  Ringing?  Lots of things it could be.  No way to tell from a 10,000m view.


Quote
Quote
Then you will be pretty much on par with an analog supply.

can you kindly explain?

A linear supply only rectifies mains voltage, filters, and regulates it if applicable; they have no switching noise besides the diodes, and that's at mains frequency and harmonics so is easily handled by a regulator.

There's nothing inherently impossible about a quiet SMPS, but they do take more effort to make quiet: you can't be lazy about layout, and may need shielding.

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Re: My PSU design ripple and noise with picture measurements
« Reply #149 on: January 05, 2022, 09:28:37 pm »
so I just hook it up as usual then zoom in to 200us or so range?

I mean, what do you really want to see or verify? 2MHz switching frequency (exactly the same as previous design) is big enough not to be shown and therefore it didn't need big inductors, yet we used 4.7uH main inductors. It also has ferrite beads integrated inside the feedback loop itself as explained later.

it is quite difficult to measure the current, i mean i can not break the circuit to insert the current measurement. and since there is nothing to see for current then maybe no need to do it.

I just don't want to do more pcb revisions for now.


I do report that the device works perfectly fine and image is very clear with no problems. 3.3v and 5v are spot on as value too.

looking at the images above, how do you compare between the 3 PSUs?

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Re: My PSU design ripple and noise with picture measurements
« Reply #150 on: January 05, 2022, 11:36:55 pm »
Hello

I have done extensive tests as required and here are the pictures: https://slow.pics/c/tXFqHF3r

please notice picture's name under it, which signifies measurement parameters.

I have added some capacitors directly at 3.3v rail output pin to gnd pin as indicated by pictures, values like 4.7n, 47n, 2x47n, 22p, and 10u elec, as well as 33u elec. It doesn't seem to have done a noticeable effect.

what do you think?

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Re: My PSU design ripple and noise with picture measurements
« Reply #151 on: January 06, 2022, 12:39:16 pm »
so I just hook it up as usual then zoom in to 200us or so range?

Why guessing?  I gave a number earlier?

~200us/div may show insight into control loop compensation, or the like.  Not that you're doing a proper load step test, it's just whatever the console draws, which... who knows, it could be doing anything?  Wouldn't it be nice to know what it's doing?


Quote
it is quite difficult to measure the current, i mean i can not break the circuit to insert the current measurement. and since there is nothing to see for current then maybe no need to do it.

I didn't say it was going to be easy to measure -- or necessarily that you have to measure it at all, but if you're looking for cause and effect, y'know... wouldn't that be a good thing to know?  Worth cutting a wire and inserting a probe, current shunt, sensor, whatever?  Or testing with an independent load of known behavior?


Quote
looking at the images above, how do you compare between the 3 PSUs?

Well, on what basis should they be compared?  Evidently they all work; is that sufficient?  What things would your potential customers want to see before buying?  What things can you test?

If I were considering buying such a thing, I would want to know that it's followed good practices.  Now, I don't expect to see a product description claim that; it should be safe to assume.  Customers have that expectation, and they're relying on your good will that it does what it says, and doesn't blow up their hardware or whatever.  It's a lot harder to test for good will, or not blowing up, but you can invest in preserving your reputation by doing electrical tests that exercise the extremes of electrical and other conditions, which should have a strong correlation with also not blowing up.

For my part, I would do at least:
- Supply voltage range test: make sure it meets or exceeds ratings, over the full input range;
- Protection, if applicable: for example if the device has reverse polarity protection, check that it works down to the rated reversal.  Similarly with transient or overvoltage protection, to the extent I need to/care to/can test it.
- Load current range test: meets or exceeds ratings, while at supply min/nominal/max; characterize the current limit / foldback / hiccup / etc. behavior;
- Load step test: output ripple voltage is within tolerance for typical load conditions e.g. 50% base, step to 100%, step back to 50% of rated output;
- EMI/RFI emissions: set up the device in a testing jig, to measure RF emissions from input and output ports.  This is particularly important for things connected to long wires/cables, AC mains, or low-noise systems.  If it's just some internal part, maybe it doesn't matter; this isn't a required step for any particular module or subcircuit (like a DC-DC converter, say), but in that case, the things that do reach those paths (long cables etc.) should have their own filtering to deal with it.  Or it can be dealt with in a case-by-case basis, perhaps the module is too noisy for the filtering in one particular system and does need to be improved, etc.

I happen to have test jigs (or know how to make my own if needed) for that last one, so it's feasible for me; conversely, I don't happen to have the equipment (signal generators, RF amplifiers) to do RF immunity testing, or transients (EFT, surge, etc.).  So for those, I follow good design practice, and hope that it works out.  (Which, I have the benefit of calibrating that experience by testing commercial products in the lab; that would be hard for you to do on this project, unfortunately.)

The next best thing, that you can do presently, for that item, is at least just looking at it on the oscilloscope.  It has the frequency response required (well, some of it anyway).  It doesn't read signals the way an EMI receiver does, but still, it's something.  Even without a test jig, the fact that when you're clipped onto it, you're seeing tiny (~us) squiggles, is proof that something's going on in there.  How many mV tall are those squiggles?  Would it be enough to interfere with a nearby radio?  (Mind, you can only test for radiointerference when you have A. a radio that operates at some frequency, and B. a radio station at that same frequency, to potentially be interfered with.  Or at best you pick up the pilot tone or buzz of the SMPS, on a dead channel, not needing B.  Trouble is, maybe you can pick up the AM and FM commercial broadcast bands; maybe you even have a SW receiver too.  But beyond that?  I mean, it's still something, but it's very spotty coverage, not representative of the full 1 to 200+ MHz range we expect an SMPS to produce.)

And no matter how hard you squint at it, you're not going to tell what's going on at those frequencies, looking at a 50ms/div trace.

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Offline BrianHG

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Re: My PSU design ripple and noise with picture measurements
« Reply #152 on: January 06, 2022, 04:40:43 pm »
Those pulses are approximately 20ns wide, or in the 50MHz region.  The right series ferrite/rf choke would prevent the propagation of that switcher EMI interference as we see the GND input trace is clean.
 

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Re: My PSU design ripple and noise with picture measurements
« Reply #153 on: January 06, 2022, 06:36:54 pm »
well thanks for your feedback, here is what I think I should do:

label it as "high quality low noise power supply replacement for dreamcast". it is of high quality for the job as it uses good parts and good design practice, went on many revisions..etc and low noise since it is noticeably less noisy than the best alternative (about x2 times) and a better than original PSU as well. I also tested it for long play hours and it went fine with very clean picture which is the ultimate purpose. not to mention that it does have a lot lower temperature than stock PSU, and it has 12v rail properly loaded in case of removing gd-drive.

as of protection, this is a duty for the used 12v wall adapter not this device. this is the case for all designs as well. also short circuit protection the same. I could design a "pro" version of it later on which takes ac directly using recom or meanwell 12v power modules but this will be very expensive and not the scope of this board. such power modules have everything inside and all protections.

I am interested into the potential issue inside the switchings... aren't they just the switcher switching itself? and since this was tested to work properly without problem we can assume it is not going to be one.

I maybe can add one ferrite bead right before the output pin which is the same type used here... but isn't adding 10nf caps better? like adding them before and after the inductor, plus the ferrite bead, and at the load pin itself?

I am open to do any change which is easy to implement in the upcoming 20 boards production batch, which won't do any problem... meaning if it didn't enhance the system, it won't break it. i believe adding ferrite bead and 10nf caps as mentioned won't make the circuit broken or unstable if it didn't enhance it.

the project should be easy and specs are simple, it works and produces low noise and low ripple when using normal 12v power adapter. that is it for me... so that people can buy it knowing it is the best choice as replacement for the original one.


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Re: My PSU design ripple and noise with picture measurements
« Reply #154 on: January 09, 2022, 09:44:09 pm »
hello,

kindly check the attached picture, it has small changes which can be done without fearing of circuit getting broken.

it is just replacing 47uf input filtering for each switcher with 1000uf, plus adding small 10nF in 3 places for extra filtering for higher speed ripple if necessary.

I can relocate stuff to fit these easily, on expense of removing some silkscreen.

i figured that ripple is coming from input side rather than the switchers themselves since they are about 2mhz while ripple is slower. so, having a significantly larger input cap (while keeping some 22uF ceramic input caps) should enhance the signal.

right now i can modify the circuit i have to add these and test them next 1-2 days since i have a lot of 1000uf smd caps, it doesn't have a footprint for sure but can be installed using very short wires and so on.

i just like to hear your opinion.

EDIT: hmm i could replace 4.7uH inductor which is the input to the 2 switchers with 10uH one (not shown in this pic), also the other 4.7uH which is the filter of 12v output rail. i found one with same footprint. however, switchers inductors should still be 4.7uH

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Re: My PSU design ripple and noise with picture measurements
« Reply #155 on: January 10, 2022, 10:22:58 am »
just a side note, i've found some small footprint 1uH inductors with high enough current.

Would it benefit if I put one of 1uH L on the output of the rail, just before one 22uF ceramic and 47uF elec. cap? plus one at the input of each switcher to act as a small pi filter with either the currently installed 47uF or the suggested 1000uF?

also, adding either 4.7uH or 10uH inductor right after the CMC and before the global 1000uF elec. cap?

oh fk! i am fking redesigning it again despite it worked fine and delivered better results than the others!!! am I ill?

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Re: My PSU design ripple and noise with picture measurements
« Reply #156 on: January 10, 2022, 06:41:33 pm »
Do not change you output circuit.  You board is working fine.  It is the 25-50MHz band switching pulses you want to filter out.
For this, you do not want to add inductors to the middle of your circuit or even add caps.  What you want is a series ferrite bead choke right at the output of your PCB before it feeds the Dreamcast.  You want a ferrite bead with as low as possible impedance to make sue you do not loose any voltage or regulation at the output, plus, a ferrite which has a significant -db signal choking capability between 25-50MHz.  This one component, I'm guessing 2 of them on the +3.3 & +5v out will prevent the migration of those tiny pulses from your PCB to the Dreamcast.

The source 12v power supply would not be the generator of these spikes as they are too high in frequency/narrow to make it down the long power cable in tact as we see in your scope shot.
 

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Re: My PSU design ripple and noise with picture measurements
« Reply #157 on: January 10, 2022, 07:21:29 pm »
So not even an extra 22uF ceramic cap at the output?

The ferrite beads I am using is Würth Elektronik 7427922808, it is already there and inside the feedback loop itself (the feature of the switching IC). how does it compare here?

from its datasheet I see it is about 8-10 ohms @ 100 MHz, but only 5 ohms at 50 mhz. it was recommended by the switcher datasheet itself.

the other recommended ferrites are: BLE18PS080SN1 and 74279221100.

which parameter in datasheet should I look for in ferrite beads to know the suitable part for 20-50 mhz attenuation? and what about my current one's capabilities?

EDIT:

I searched and found these alternatives:

Z0603C280APWST -> very cheap (30% of the one used currently). about 28 ohms @ 100 MHz, estimated of 21~26 ohms from 20~50 Mhz.

BLM18KG300TH1D -> very cheap as well, labelled as 30 ohms @ 100 Mhz. website shows 15-22 ohms from 20-50 mhz.

FBMJ2125HS420-T -> probably cheapest. 42 ohms @ 100mhz. 32~38 ohms at 20-50mhz. is this the best out of these suggestions? however this is 0805 which requires some modifications to fit it... original one was 0603

if these are accepted, can they replace the one already used inside switching regulator's loop? this will enhance the price and looks like it will also enhance performance.







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Re: My PSU design ripple and noise with picture measurements
« Reply #158 on: January 10, 2022, 08:51:27 pm »
None of these specify DC bias, so it's not obvious if they would be suitable.

At such frequencies, layout is critical.  It's very difficult to say offhand how much is present by inspection alone.  Why do you refuse to measure it?

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Re: My PSU design ripple and noise with picture measurements
« Reply #159 on: January 10, 2022, 09:43:19 pm »
None of these specify DC bias, so it's not obvious if they would be suitable.

At such frequencies, layout is critical.  It's very difficult to say offhand how much is present by inspection alone.  Why do you refuse to measure it?

Tim

can you show me where is the dc bias in another one if you know?

how can i measure it? didn't i take all measurements?

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Re: My PSU design ripple and noise with picture measurements
« Reply #160 on: January 11, 2022, 04:18:19 am »
Apologies, I had checked your last link after your last reply after it but it seems either it wasn't updated by then, or my cache didn't update, in any case I only saw the 50ms/div measurements.

So, the thing about the ~10ns pulses.  Do they show similar magnitude when probing ground to ground?  Any ground, any connector?  If so, it's more common mode than the differential mode you think it is.  For which, differential filtering will accomplish nothing, and the question of ferrite bead is moot.

At a guess, the input won't have much of this noise (at least when probed by itself), due to the CMC.  The question is then, which connectors/grounds is the noise between, and should that be solved by cutting ground, rerouting traces, adding CMCs, etc.?

Or it may still be differential, suggesting fairly poor performance of the inductors I think, as the layout isn't that bad.  Maybe you just need better inductors, or another LC stage with a smaller value like 0.47uH then some 0.1uF's, say.


Bias curves are shown in the datasheet, or mfg supplementary (characteristic) curves, if available.  Most do not provide them.  Laird is the most reliable, having bias curves on almost all beads in their catalog.  Wurth sometimes does, as was in this case:
https://www.mouser.com/datasheet/2/445/74279221100-1720641.pdf

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Re: My PSU design ripple and noise with picture measurements
« Reply #161 on: January 11, 2022, 06:35:57 am »
so I should go and do the same probing but try to probe another ground points? like the negative of ch2 is on output ground pin while positive of ch2 is on other ground pins of the circuit?

you can see all pictures here: https://slow.pics/c/tXFqHF3r > there is a 500ns/div picture and others, please re-check. name of each picture is under it.

inductors are the maximum size for the switchers, 4.7uH. suggested inductors in datasheet are very very expensive.

I can add an extra stage as suggested earlier, will be 1uH inductor + 22uF + the 47uF elec cap since it should be the final one before the connector. or add another ferrite bead just before the connector. if 22uF is not suitable, I have 1uF ceramic used elsewhere, so I can use it here. such components are very cheap and can be added easily. but why very small inductor and cap size for extra LC stage?

I still want to think about making input filtering to the switchers a bit bigger... or add an inductor right after the main CMC, or making main inductor filter for the switchers input 10uH instead of 4.7uH...etc. what do you think? a better way is to remove 2 of 22uF ceramics and replace them with 47uF elec. this is half the price and better performance since input voltage is 12v and the 22uF 1206 ceramics will surely suffer from dc bias. then add another 47uF to be the total input filtering per 1 switcher is 3x 47uF elec + one 22uF ceramic + 10nF (bypass at pin). instead of 3x 22uF ceramics + 1x 47uF elec. + 10nF. how about that

we already used a CMC at the input and it did great to suppress much of the earlier noise and it helped eliminate 50hz stuff. adding another one will be expensive unlike the extra LC stage.

so maybe it can be like this: switcher -> 4.7uH (main L) -> 4x 22uF -> main ferrite bead -> 3x 22uF ->1uH (extra L) -> 1uF -> 47uF elec. -> 10nF (already exists). with an optional ferrite after this.

still, what do you think about the suggested ferrite replacements? they are cheaper and still have more Z at frequencies.

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Re: My PSU design ripple and noise with picture measurements
« Reply #162 on: January 12, 2022, 04:35:54 pm »
the funny thing is that TPS62913 is out of stock and will be in stock in September!!

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Re: My PSU design ripple and noise with picture measurements
« Reply #163 on: January 17, 2022, 06:59:56 am »
I would like to point you to this image: https://i.slow.pics/31fiYciR.png (taken from all photos here: https://slow.pics/c/tXFqHF3r)

it is 500nS time base, and shows about 2 MHz pulses of about 17 mV p-p. this is clearly the switcher's switching frequency which is about 2.2Mhz.

hmm can we choose a ferrite bead which has a lot of impedance at 2 mhz to solve this?

this one (https://www.digikey.com/en/products/detail/w%C3%BCrth-elektronik/78279221281/14669530) seems nice with lots of impedance but the dc bias makes it about 1 ohms @ 2 mhz frequency when current is about 3 amps. so it becomes useless?

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Re: My PSU design ripple and noise with picture measurements
« Reply #164 on: January 17, 2022, 09:45:29 am »
I would like to point you to this image: https://i.slow.pics/31fiYciR.png

it is 500nS time base, and shows about 2 MHz pulses of about 17 mV p-p. this is clearly the switcher's switching frequency which is about 2.2Mhz.
Those pulses are in the ~50MHz frequency range.  They may be happening at a period of the switcher's 2.2MHz, but as you can see they are tiny single cycle ~50MHz oscillation happening twice every 500ns, a single pulse going up, and a single pulse going down.

If it was a 2MHz signal, you would see a single fat sine wave going up and down, where each pulse would be a fat wide 250ns high and 250ns low.  This is not what we are seeing.  This is why choosing the right filter is important here and optimiziog your output filter for 2MHz might end up filtering nothing letting that higher 50MHz pulse go right through.  You want a filter where the '50MHz' component will be something like 100 or more ohms series resistance so any 0.1uf output cap will divide that component by a factor of 100 or more while the lower frequencies like below 2MHz will be a short of 0.01 ohms or less.
 

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Re: My PSU design ripple and noise with picture measurements
« Reply #165 on: January 17, 2022, 05:25:14 pm »
ok so adding 100nF cap can solve it? I will try that soon, I have some 0.1uf elec caps around

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Re: My PSU design ripple and noise with picture measurements
« Reply #166 on: January 17, 2022, 08:05:06 pm »
Take a look at your capacitor impedance charts.  You want to choose capacitors with the lowest impedance in the 20-50MHz range.  This may be a smaller value than 100nf.  You need the true specs from a cap company with true readings.

The same goes for the series ferrite bead or inductor before that cap.  You want as close to 0 ohm as possible, but, at 20-50Mhz, you want as high impedance as possible.
 

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Re: My PSU design ripple and noise with picture measurements
« Reply #167 on: January 17, 2022, 08:59:28 pm »
For supply evaluation, I always add an AC-coupled noise amplifier on the board – say x20 or x50, and an active rectifier and active peak detector. That way it’s easy to see ripple on any oscilloscope, and measuring peak and average ripple/noise can be done with a multimeter. But those three circuit functions need to be also well designed and fairly broadband (say 100MHz bandwidth) – and their layout is critical too. So it’s a chicken and egg problem: you have to already know quite a bit to design all that. For ripple itself, you’ll do fine with a lower bandwidth amplifier, since otherwise the scope isn’t sensitive enough, so even 10MHz is better than nothing. That still calls for an op-amp with 100Mhz GBW, and you’ll need two stages of gain. And it that opamp is quite hot when idle, you know you got oscillation – then just compare the op amp’s supply current with the quiescent value in the datasheet. You’ll want current measurement shunt resistors installed on the PC board to avoid messing with multimeter’s ammeter series connection. Heck, that amplifier could be discrete, to save on cost. But without a scope it’ll be hard to make sure it all works. All amplifiers can oscillate and their DC readings taken with a multimeter will look great, but it’ll be misleading. And some wideband amplifiers just run hot by design – especially the older video amps.

You’ve got many pointers from other replies. One thing I’d add: whatever “layout examples” the manufacturer provides don’t mean that you can just copy them and are guaranteed stuff will work. It still takes understanding of what the layout decisions mean and why they were made. Those are handy “sanity check” references for experienced engineers. For novices who can’t but copy without understanding, they are only mildly helpful.

Furthermore, in switching supply design, the non-ideal properties of components do matter, and things like ceramic capacitor dielectric type and ESR and SRF (self resonant frequency) of any capacitor type do play an important role.

And then, just looking at the size of that switcher chip: the inductor physically looks like it’s way too big. Those things usually scale together, so the physical size of the switcher chip and that of the surrounding passives go together at least roughly. Not always, but such big disparity is a red flag.
 

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Re: My PSU design ripple and noise with picture measurements
« Reply #168 on: January 18, 2022, 10:21:52 am »
I didn't quite understand last point about capacitors ratings of impedance vs frequency. But know that I opted for caps from Lelon brand since they are good well known and available for JLCPCB, that is for elec. caps. for ceramics, I get what is available on LCSC and JLCPCB SMT service.

However, for ferrite bead, I get it from Digikey\Mouser from well-known brands... I posted few suggestions which has quite good impedance at 20-50mhz which could replace the originally recommended by chip manufacturer.

as for inductor size, it is 4.7uH and no way I can find one 2x2mm (size of the switcher). Recommended inductor is smaller than what I got for sure but physical small size isn't important to me, but price is. LCSC inductors are a lot cheaper than say Pulse branded ones and do the same. I got ones with greater ratings than required to eliminate any chance of margins.

I didn't blindly follow the example layout but rather did my own using best practices. You can find pictures of it in previous replies, people here helped doing it.

So to sum-up, here are some suggested solutions:

1- keep all the same, and go for a 2nd ferrite bead using one of the suggested above after the final 47uF elec. cap. a bead which has good impedance at 20-50mhz as the parts I listed above.

2- add another LC circuit comprised of 1uH inductor (small size) + 22uF caps as PI filter. meaning, split the output caps to be before and after the added L. ensure 47uF elec. cap to be the absolute final before the connector.

3- same as 2 but also add another ferrite bead.

4- same as 3 and 2, but add 10nF or 100nF caps next to big caps.

note: i am ok for getting one nicely branded cap but it should be say 0805 so I can hand solder it. one extra BOM line won't ruin the entire design economy. Please check the inductor I chose too.

which do you think should we go with? if not, please suggest a practical move i can use.

Notice that I am fine with <9mV of total ripple but just wanted to filter out the high frequency noise spikes. I don't think it will affect the final output of the system but still should be solved if possible. this design is already x2 times better than all other solutions. also, better in terms of ripple than original one, but worse in noise... original one doesn't have any noise spikes at all.

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Re: My PSU design ripple and noise with picture measurements
« Reply #169 on: February 13, 2022, 07:37:06 am »
Take a look at your capacitor impedance charts.  You want to choose capacitors with the lowest impedance in the 20-50MHz range.  This may be a smaller value than 100nf.  You need the true specs from a cap company with true readings.

The same goes for the series ferrite bead or inductor before that cap.  You want as close to 0 ohm as possible, but, at 20-50Mhz, you want as high impedance as possible.

I wanted to make a final revision (hopefully) so I am interested in your suggestion, which is after the final 47uF elec. cap... adding a series ferrite bead and a 100nF or so to ground.

So I am trying to search for values similar to what you have explained, so can you help?

I found this cap and here is its data. click characteristic graph -> frequency graph -> |Z|

I found its lowest Z is at 25 MHz, but this is the resonance frequency right?

what do you think?

Also, here is another one which is 10nF: GCM155R71H103KA55D this one has 0.5-0.2ohms at 25-50mhz and its resonance frequency is about 90mhz.


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Re: My PSU design ripple and noise with picture measurements
« Reply #170 on: February 23, 2022, 11:15:10 am »
I posted the question to TI support to see if they have a good recommendation, plus asked them about exceeding maximum output capacitance of 200uF.

Looking forward to your comments on my previous reply.

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Re: My PSU design ripple and noise with picture measurements
« Reply #171 on: February 23, 2022, 03:04:05 pm »
plus asked them about exceeding maximum output capacitance of 200uF.
I'm not sure simple increasing a capacitance at the output will help with noise or spikes. It doesn't work like that in real life. You just have to make some experiments with different types of caps of a low value (1-47 uF), consider playing with electrolytic caps of a general type with high ESR too.
« Last Edit: February 25, 2022, 05:15:28 pm by Vovk_Z »
 

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Re: My PSU design ripple and noise with picture measurements
« Reply #172 on: February 23, 2022, 06:07:24 pm »
And like I said. It might be common mode noise still.  It is impossible to tell without a proper setup, free from conflating sources (from the power adapter, load, etc.), and preferably in a jig that gives standardized conditions (typically LISNs over ground plane).

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Re: My PSU design ripple and noise with picture measurements
« Reply #173 on: February 23, 2022, 06:39:37 pm »
And like I said. It might be common mode noise still.  It is impossible to tell without a proper setup, free from conflating sources (from the power adapter, load, etc.), and preferably in a jig that gives standardized conditions (typically LISNs over ground plane).

Tim

I do appreciate your pro tips and setup but I am not that advanced nor the product itself. I mean, we came a really long way to achieve this low noise level after much help... just one more issue remained. I will be very happy if we could attenuate it by any factor for now.

TI chip will be in stock in May but my PCBway can get them now for 10$ per IC... so I can make one more prototype and 1 assembled board.

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Re: My PSU design ripple and noise with picture measurements
« Reply #174 on: March 20, 2022, 05:23:17 pm »
Hello,

I have been idling for a long time, I thought of some minor changes could be done to enhance the thing with little to no cost. I thought of changing the CMC to a better one, here are the candidates I searched for:

https://www.digikey.com/en/products/detail/pulse-electronics-power/PA4339-102NLT/9659623 -> 1.02k ohms @ 100MHz, about 600 @ 20mhz and 1000 @ 50 mhz. this is a massive upgrade of attenuation from previous one  (DLW5BTM501SQ2).

https://www.digikey.com/en/products/detail/tdk-corporation/LCV70-701-2PL-TL00/11682555 -> 700 ohm @ 100 MHz. Upgrade from old one but the first candidate is better IMO. Unless Z @ freq. is not the only factor.

https://www.digikey.com/en/products/detail/w%C3%BCrth-elektronik/744237152/14011659 -> better than both but higher price.

^ all this assuming 12v @ 3amps of absolute maximum, reality is less.

original CMC was noticeably cheaper, these are easily 0.5~0.8$ more in price. So I thought of removing some inductors and caps here and there to save some cost, and put only one big main filter inductor instead of one per switcher. What do you think of that? so something like this:

12v -> new CMC -> elec. caps (47uF x 2) -> big inductor (cheap one but big) -> 1000uF elec cap. then input to each switcher will get 2 or 3 47uF caps + 2 22uF ceramics. while the 12v output only has like 1 47uF since it is not really used much.

or instead of one main filter cap I put one per regulator but leave the 12v without inductor?

I thought of this due to the harmonics seen are mostly common-mode as many here agreed, plus getting more diff. inductor filtering should help.

I am open to suggestions.


EDIT:

inductors selected for now:

100uH: https://lcsc.com/product-detail/Power-Inductors_TAI-TECH-TMPC1206HP-101MG-D_C357256.html
33uH:   https://lcsc.com/product-detail/Power-Inductors_PROD-Tech-PSPMAA1040H-330M-ANP_C436575.html
10uH:   https://lcsc.com/product-detail/Power-Inductors_PSA-Prosperity-Dielectrics-MCS0630-100MPY1_C2937094.html

so putting one 100uH as main filter, then just bulk caps before regulators seem good or putting 33uH per regulator without main L. what is best? the 33uH is slightly more expensive than 4.7uH one! still gonna need a 4.7uH for the switcher itself as indicated by datasheet.

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Re: My PSU design ripple and noise with picture measurements
« Reply #175 on: November 13, 2022, 12:44:27 am »
Hello,

boards arrived, tested and it works perfectly fine as intended except for one thing.

Well, ripple for 3.3v is about 5mv p-p which is awesome! you can add the noise sparks and it become less than 10mv p-p. I consider this a win!

however it is not the same for 5v rail, which can go to 40mv p-p sometimes!

I figured it could be due to layout, therefore I attached the layout pics...

any suggestions??

I will make another board for more testing, which originally was to test putting 3 vias for routing the 5v signal as seen in attached image but now I need to see what to do really.

I highly appreciate your suggestions

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Re: My PSU design ripple and noise with picture measurements
« Reply #176 on: November 13, 2022, 06:41:44 am »
here are the problems which I think might have caused this bad 5v rail despite 3.3v is perfect:

1- long travel of 5v signal from first stage filtering (C9 and others) to ferrite bead FB3:

as mentioned, in manufactured design the signal goes under 3.3v signal by only 1 via not 3... I made them 3 vias later on.

however, 3.3v signal is very short and direct as seen.

TI rep engineer didn't like placement of the ferrites and their signals being under one another, basically that whole area. they called it "cross talk" and "overlap" due to high frequency resonance of the ferrite beads.

what do you think?

2- the 5v rail filters are near the 12v rail which is minimally filtered:

not so much there but still listed this as a possibility. the 12v rail signal is at the very right of the board but somehow near the 5v filters.



I will post waveforms soon but trust me that 3.3v total ripple noise figure is about 3-10mv p-p which i assume the best one can get from such buck designs.

my possible solution which I started to accept is to make the board 70mm length x 50mm width instead of 50x50. the 20mm of length will help me re-distribute the ferrite beads and final filter caps to make connections to 1st stage extremely short and direct + very far from each other. so no cross talk or anything to be feared. also, will make me shift the entire thing to the left side which makes everything very far from 12v signal line


is my analysis good?

what do you think?

I was very happy for 3.3v rail results but got disappointed for 5v ones... really thought i was ready for production...! very hyped! now more testing boards and time has to be consumed but I ask all these questions to make sure the next test board is the final one.

best regards

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Re: My PSU design ripple and noise with picture measurements
« Reply #177 on: November 13, 2022, 06:58:47 am »
Possibly this is a candidate for a slotted ground,



Pink arcs: switching currents circulate under the regulator.  This is mostly local, but some leaks out into the surrounding ground plane -- no conductor is ideal.

Pink 'U': a slot here would prevent currents from flowing into the connector and filter area.

Downside: the plane suddenly stopping here, means whatever current would've been carried by it, is instead wide open and exposed in the slot.  This can make induction worse, for example.  (Keep traces at least a board thickness away from the slot.)  Maybe there's more voltage across the slot, than there was across the plane before.  This could increase common mode noise (even given the input CMC).

The extra 12V trace would be spanning across this slot, carrying 100% of the voltage on one side of the slot, across.  It must be filtered locally, with an inductor to absorb that (AC) voltage drop, and a capacitor to firmly [AC] ground it again.

To explain further: the pink arcs represent current flowing under the regulator, at least very vaguely.  Normally, that current is "shorted" out (no short is ideal, but copper is nearer to a short than say air is), so the voltage drop is small, and confined locally (read: dropping inversely with distance from the source, or probably faster than that, up to an exponential drop with distance).  With the slot, the voltage drop is not shorted out, but left hanging.  Which puts some voltage on one side of the slot, that isn't present on the other.  Hence, common mode voltage appears between the two sides.

But the best solution is to optimize out all the extraneous capacitors (I think you will find you get the same noise level with a fraction as many), place the regulator off to the side or in a corner where its currents can be better localized (using the natural board edge as a slot, as it were, but more to the point, also routing in/out from just one side of the region), and joining the connectors as well as possible (solid ground plane between them) and filtering local to them.  Such a layout will take more blank PCB space for noise separation, which will be obtained by optimizing the filter components.

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Re: My PSU design ripple and noise with picture measurements
« Reply #178 on: November 13, 2022, 07:29:19 am »
I didn't really understand all that you said but I kinda understood that "U" that you put made a slotted ground meaning 2 ground plains separated which prevents currents from circulating properly which forces them to travel near or under the 5v rail signal (= along the slot).

however, the arcs you put are not an issue IMO because most of them are feedback resistors network and one for some internal regulator cap... all grounded properly as seen while switching currents should come only from one pin per rail and as seen coupled to ground with multiple vias. how can this be an issue?

there cannot be any modification to the 12v long trace since this is how the board and product shape is. assume we got the ground plain to be properly done, will this trace do any harm without putting an extra inductor to it? I can put caps though.

I'd like to remind you that the bottom layer is all ground with minimal traces so i think even if the slot exist on top layer, the bottom ground should be there. or am I wrong?

I have followed datasheet and rep engineer layout guidance for the regulator, besides the issues i spoke of. I don't know what caps you speak of, do you mean first or 2nd stage filtering?

my next plan is to make length 70mm and change the layout as drawn in attached image.

this way there will be no ground slots or disconnections but rather very short and direct connections for the rails with 0 cross between them as they will be very far.

is this what you meant?


note that the capacitance are sized according to design and datasheet calculations and so on, don't really recall exactly but be sure they are correct value.


what do you think?

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Re: My PSU design ripple and noise with picture measurements
« Reply #179 on: November 13, 2022, 09:17:45 am »
I didn't really understand all that you said but I kinda understood that "U" that you put made a slotted ground meaning 2 ground plains separated which prevents currents from circulating properly which forces them to travel near or under the 5v rail signal (= along the slot).

Not really two. Different regions of the same. The pour will still be solid around the left (where the 'U' does not extend).


Quote
however, the arcs you put are not an issue IMO because most of them are feedback resistors network and one for some internal regulator cap... all grounded properly as seen while switching currents should come only from one pin per rail and as seen coupled to ground with multiple vias. how can this be an issue?

You "don't really understand", yet you deny the possibility?  (Namely, that currents flow over an extended range, a fuzzy, broad path, not a straight line.)

Wait, do you think current follows the "path of least resistance"?  As in, the infinitesimal narrowest and shortest possible path between two points?  Fucking hell that phrase is so harmful.  It should not be repeated, it so easily leads to such conclusions.  I wish people would expunge the phrase from history itself!

Needless to say, current does not follow such a foolish path.  It's a field, it spreads out along conductors, particularly between their facing sides (at AC).

Current flow in the area has little to do with which exact components are there.  I don't care about the feedback resistors.  They're irrelevant to this flow.  The primary switching loop is between the chip and the bypass caps (above it).  Currents can nonetheless extend down even below the chip.  It is my guess that this is the effect at work here.

There are other tests that could be done to confirm this, but I'm remembering now, it's training cats to pull teeth to get you to test anything the least bit confusing... so, nevermind.


Quote
I'd like to remind you that the bottom layer is all ground with minimal traces so i think even if the slot exist on top layer, the bottom ground should be there. or am I wrong?

...All layers...

As in, you could literally saw through the board, and maybe actually demonstrate exactly this with the PCB you have.  I might not recommend that, for a variety of reasons, but from such a process, that's where the copper would be (and wouldn't).  Removing copper on all layers, and leaving PCB material (FR4), is fine there.

But if you're going to the trouble of a new board, I would again suggest a better layout emphasizing the grounding between connectors.


Quote
I have followed datasheet and rep engineer layout guidance for the regulator, besides the issues i spoke of. I don't know what caps you speak of, do you mean first or 2nd stage filtering?

Reps don't know anything, it's blind luck if they are helpful at all with EMC issues.

More exactly, they aren't particularly different, as a class, from any other EEs.  Among which, EMC knowledge is rather spotty at best, and full of partial or mis-conceptions.


Quote
my next plan is to make length 70mm and change the layout as drawn in attached image.

this way there will be no ground slots or disconnections but rather very short and direct connections for the rails with 0 cross between them as they will be very far.

is this what you meant?

I can't tell what components are supposed to be here.  I guess the one connector is shown.  Where are the others?

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Re: My PSU design ripple and noise with picture measurements
« Reply #180 on: November 13, 2022, 10:00:15 am »
Quote
You "don't really understand", yet you deny the possibility?

it is that I understood you meant something related to feedback resistors since arcs were on them... now i know you only meant switching node currents from switcher to inductor. this I agree with you on it for sure.

Quote
Wait, do you think current follows the "path of least resistance"?

I know this famous line is not really that straightforward. I saw many videos on return path current and so on and how to optimize layout for it.

Quote
But if you're going to the trouble of a new board, I would again suggest a better layout emphasizing the grounding between connectors.

this is good and practical to do, can you tell which connectors exactly? I can start tonight especially if I extend the length of the board by 20mm which will make really nice space to work.

Quote
Reps don't know anything, it's blind luck if they are helpful at all with EMC issues.

this was my thought as well but at least I wanted to involve someone to take a look at my layout. she did emphasize on the "cross talk" between the two rails due to overlap of the ferrites as i mentioned above. do you think it is an important issue?

Quote
I can't tell what components are supposed to be here.  I guess the one connector is shown.  Where are the others?

hmm i guess I put arrows to tell which is which. it is a mere rough drawing... for example that half-T shape is for first stage capacitors, I draw it like this since it is the same way I layed them out if you return to the layout picture. the bold line indicates power signal path... now it is straight and short with no cutting of any ground or making slots (to my knowledge).

FB is ferrite bead, 2nd stage is for 2nd stage filtering caps which originally were at the bottom left of the design... now in this suggested drawing they are spaced well to ensure no cross talk.. etc.

any suggestions?

Quote
There are other tests that could be done to confirm this, but I'm remembering now, it's training cats to pull teeth to get you to test anything the least bit confusing... so, nevermind.

I have owon isolated usb scope and nothing more.

i was thinking to make some tests like putting extra elec. caps, or remove the 12v rail trace (scratch it from its origin) so that I see if it is the one affecting the 5v rail... also thought of removing 3.3v rail ferrite bead to make only 5v rail exist to see if ferrites affect each other... hmm also maybe take scope measurements at the end of stage 1 filtering caps for both rails to confirm that the problem happens in later stages as i suspected, namely the long 5v trace from 5v first stage filters to 5v ferrite bead.. the one which made the slot to begin with.

I am open to suggestions... to make sure the new test board is finally the last revision. and always thanks for your continuous support.


EDIT: I made another rough drawing for the suggested new layout. sorry right now in work i don't have my laptop to do proper kicad layout.

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Re: My PSU design ripple and noise with picture measurements
« Reply #181 on: November 13, 2022, 05:49:56 pm »
I've been thinking if instead of the 5 2nd stage 10uF ceramics... I put 4 ceramics the same + 1 22uF elec. cap + 1uH inductor to further smooth it out. is it better?  ofc, using the better layout.

so it becomes:

1st stage caps -> the ferrite bead -> 2x 10uF ceramics -> 1uH L -> 1x 10uF ceramic + 1x 22uF elec. cap near the output pin.

for your opinion.


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Re: My PSU design ripple and noise with picture measurements
« Reply #182 on: November 13, 2022, 08:35:03 pm »
I have done extensive measurements as seen here: https://slow.pics/c/NlypkqhL

each picture has its own title so you can know what it is.

I noticed it delivers 25mv p-p at full load for 3.3v which is, unfortunately, similar to another cheaper PSU on the market... so it would not make sense to make this one. I wonder why really... that psu is very basic without filtering at all just 33uH + 100uF or so at the output of a generic buck regulator. previously I said 3.3v delivers 5mv but that was at very light load.

one thing I noticed with this design is that signal before inductor is better than after 33uH inductor, which is weird really. it is supposed to be better and smoother.

also it gets worse at the switcher input pins themselves, which is after the ferrite beads and some filter caps.

so assume i removed the 2 input ferrite beads and the inductor, then tested it... do you expect better result overall? since input noise is a critical figure and main cause for output noise level. but most importantly i wanted to understand why this happened in the first place.

for your kind help, I am a bit frustrated after all that huge effort.

Notice that this design uses TPS54394 instead of the TPS62913 initially used with first version of this circuit.

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Re: My PSU design ripple and noise with picture measurements
« Reply #183 on: November 13, 2022, 09:03:09 pm »
it is that I understood you meant something related to feedback resistors since arcs were on them... now i know you only meant switching node currents from switcher to inductor. this I agree with you on it for sure.

Ah, OK.


Quote
this is good and practical to do, can you tell which connectors exactly? I can start tonight especially if I extend the length of the board by 20mm which will make really nice space to work.

Any connectors with wires.

Which... is what connectors are usually for.

But more particularly, connectors with grounds connecting to other things.  Outside environment.  Floating fan connections, say, probably not so much, but input and output, especially yes.


Quote
this was my thought as well but at least I wanted to involve someone to take a look at my layout. she did emphasize on the "cross talk" between the two rails due to overlap of the ferrites as i mentioned above. do you think it is an important issue?

External field of ferrite beads is small.

Beads per se, are probably not what you want here anyway (they saturate under DC bias), but ones that big are probably okay.  A regular inductor like 1uH or so would be more compact.

Coupling between the beads is irrelevant; what matters is their absolute impedance, and some coupling between those impedances makes no difference.  Well, if it was like 50%+ coupling, that'd be weird and probably bad, but that's not going to happen on board even with unshielded spool style inductors.

Coupling between beads and switching inductors, more important.  I'd keep at least one inductor width between the inductor and the filter ones.  Which is a fine place to put capacitors.

Like, this would be feasible:



All the switching currents cluster tightly around the regulator, at great distance to the connectors; probably the slot is still better to use, and that keeps current away from the between-connectors path.  Think in terms of a 'T' section, with the top of the 'T' being the path between connectors, and the regulator being placed on the stem.  One side of the 'T' just happens to be bent around (towards the bottom, with the long connector), but topologically that makes no difference.


Quote
hmm i guess I put arrows to tell which is which. it is a mere rough drawing... for example that half-T shape is for first stage capacitors, I draw it like this since it is the same way I layed them out if you return to the layout picture. the bold line indicates power signal path... now it is straight and short with no cutting of any ground or making slots (to my knowledge).

Oh, so like as-is, but in a more vertical section.  Yeah, that avoids the slot for example.  It still puts the regulator between connectors though.


I have done extensive measurements as seen here: https://slow.pics/c/NlypkqhL

each picture has its own title so you can know what it is.

"Extensive" yeah but they're all at uselessly large scale (10ms+) so I don't have a clue what the actual EMI is like.  And you didn't take a common mode measurement (between connector grounds, or ground and oscilloscope) so it's impossible to tell how much the CMC is doing, or how much DM or other filtering is really needed.

Unless those have been added, I haven't checked since last time.

Tim
« Last Edit: November 13, 2022, 09:06:53 pm by T3sl4co1l »
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Re: My PSU design ripple and noise with picture measurements
« Reply #184 on: November 13, 2022, 09:46:38 pm »
Quote
Any connectors with wires.

Which... is what connectors are usually for.

But more particularly, connectors with grounds connecting to other things.  Outside environment.  Floating fan connections, say, probably not so much, but input and output, especially yes.

here i have that bottom right connector which is board-to-board connector. nothing else, besides the one in left side which is just the 5v rail as an extra connector for modding.

what is my mistake here and how you suggest i fix it? does it have to do with bottom right connector having bad ground path to the regulator ic?

____


your suggested layout might not work due to the regulator IC itself having the 2 output stages on opposite sides, please check it up: TPS54394.



so to sum up your suggestion, you want me to keep L and its first stage caps near the IC which is already done... however, you want me to move the 2nd stage (starting with bead) away from the main inductor... as far as possible so that no field or coupling happens... correct?? hmm I think the beads and 2nd stage are kinda far from main L... but do you mean that L and first stage itself are close to the output connector itself??

are you sure 12v trace won't cause problems despite traveling all that distance under the filtered clean rails? also the 3.3v and 5v themselves, is it ok to travel that long?

btw here are pics for the actual board: https://imgur.com/a/6ANuRwu   < now you see everything.

and here are the key components:

common-mode choke: PA4339.132NLT
ferrite beads: Fair-Rite 2773021447
main filter inductor: inductor_MCS0630-4R7MN2_7.3x6.6 (4.7uH from LCSC since the ones in datasheet and eval board are expensive)
33uH inductor: LCSC C182163



now for the slot, it kinda makes sense. i can just make a no copper zone in kicad. but we still need to see how the switch ic to be placed since as i said its inputs are from both sides not like you drew it. the slot you suggested forces the current not to go from switcher ic to the connector.


do you think I need to get the eval board (https://www.ti.com/tool/TPS54394EVM-057) and test its actual performance? or make another version myself with your guidance? I saw the eval board give about 15mv p-p which is still not 10mv i want.


since the main L is our biggest problem, they have 2.2uH and I have this 4.7uH. is mine that much worse?

actually if this is the main cause, I can invest in getting a really nice coilcraft\tdk\pulse-electronics\etc.. inductor and shave off some unnecessary stuff like maybe the input 33uH inductor and the 2 input ferrites... this could be kinda financially ok if it boosts performance.


 ___

as for measurements, kindly tell me what to measure and at which conditions and I will do them tomorrow.


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Re: My PSU design ripple and noise with picture measurements
« Reply #185 on: November 14, 2022, 07:28:36 am »
anyone knows how to cancel out the noise of the probe before using it? I mean when the probe is not connected to anything... it still displays some waveform which I think affect real measurements.
Probably only when set to high sensitivity and it's mains frequency or some local noisy SMPS.
Just normal shit you need to work with or ignore.

the problem is that I need to measure power supply noise and ripple to below 10 mv which is why I need to null this.

so there is no solution or workaround?
read jim william's app note, tektronix probe primer abc etc on how to deal with low level noise measurement. use 1x probe, short cable etc is key.. as jim said, the best probe is no probe.. there is no such thing as to cancel noise of passive probe, you probably started with unshielded, hence crappy passive probe in 1st place, solution is get decent brand probe. I saw earlier suggestion to use diff probe, i dont know how that helps as diff probe is such noisier in itself. And with cmrr and phase mismatch issue, you probably get junk reading, as i believe you already figured out. Ac coupled 1x probe to dso is the key when 10x passive probe is not reading it anymore, no need fancy or active probe.. btw I'm also working on similar smps noise issue and carefull pcb layout, except mine is variable output for preregulation purpose. I'm getting there, after changing inductor value, i get 40 to 60mVpp on linear output during switching. I'm spinning another pcb version with more carefull layout hopefully to get better noise performance.. i have this hypothesis of 'the rain of noise bandwidth' where each bw will take different path from hi freq returning along signal path (least reactance)  to low to dc freq returning in straight path (least resistance) or rain of 'coupling' or 'crosstalk', electromagnet 101.. when current move in circle, em induced and hence current on the other intersecting tracks... gnd plane is a 'circuit', not a 'plane' as we might have think. if you can avoid this 'rain in the return paths' in pcb layout, then its better, if not, i think i need to provide umbrella, ie slot(s) in gnd plane to steer away this rain of noise.. but care not to run signal or power on top of this slot.. you can google rules on slot in gnd plane. Ymmv.
« Last Edit: November 14, 2022, 07:42:33 am by Mechatrommer »
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Re: My PSU design ripple and noise with picture measurements
« Reply #186 on: November 14, 2022, 08:23:18 am »
anyone knows how to cancel out the noise of the probe before using it? I mean when the probe is not connected to anything... it still displays some waveform which I think affect real measurements.
Probably only when set to high sensitivity and it's mains frequency or some local noisy SMPS.
Just normal shit you need to work with or ignore.

the problem is that I need to measure power supply noise and ripple to below 10 mv which is why I need to null this.

so there is no solution or workaround?
read jim william's app note, tektronix probe primer abc etc on how to deal with low level noise measurement. use 1x probe, short cable etc is key.. as jim said, the best probe is no probe.. there is no such thing as to cancel noise of passive probe, you probably started with unshielded, hence crappy passive probe in 1st place, solution is get decent brand probe. I saw earlier suggestion to use diff probe, i dont know how that helps as diff probe is such noisier in itself. And with cmrr and phase mismatch issue, you probably get junk reading, as i believe you already figured out. Ac coupled 1x probe to dso is the key when 10x passive probe is not reading it anymore, no need fancy or active probe.. btw I'm also working on similar smps noise issue and carefull pcb layout, except mine is variable output for preregulation purpose. I'm getting there, after changing inductor value, i get 40 to 60mVpp on linear output during switching. I'm spinning another pcb version with more carefull layout hopefully to get better noise performance.. i have this hypothesis of 'the rain of noise bandwidth' where each bw will take different path from hi freq returning along signal path (least reactance)  to low to dc freq returning in straight path (least resistance) or rain of 'coupling' or 'crosstalk', electromagnet 101.. when current move in circle, em induced and hence current on the other intersecting tracks... gnd plane is a 'circuit', not a 'plane' as we might have think. if you can avoid this 'rain in the return paths' in pcb layout, then its better, if not, i think i need to provide umbrella, ie slot(s) in gnd plane to steer away this rain of noise.. but care not to run signal or power on top of this slot.. you can google rules on slot in gnd plane. Ymmv.

I think my Owon VDS1022I came with these along the probes themselves:



I mean the spring ground item (don't recall its proper name).

I guess this is the best I have right?

in my design I got final 3.3v output of about 25 mv p-p ripple which is similar to another cheap design, which frustrated me since I wanted to do better... to reach <10 mv p-p. the 5v rail is worse, it is +30 mv p-p with lots of noise rather than ripple.

weird thing is that the other cheaper design showed similar behavior of 5v rail being noisier while 3.3v rail just ripple.


the PSU is for Dreamcast and the main power is for 3.3v rail (2.5~3 amps) while 5v rail not so much (maybe < 0.5 amp).

what do you suggest for routing and other optimizations?

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Re: My PSU design ripple and noise with picture measurements
« Reply #187 on: November 14, 2022, 08:57:11 am »
I mean the spring ground item (don't recall its proper name).
I guess this is the best I have right?
yes thats your best at cheapest cost and easiest quick way. probe very close to output node and ground plane. here https://www.analog.com/media/en/technical-documentation/application-notes/an101f.pdf (read carefully Appendix C) jim is using single ended pre-amplifier to make measurement, so you may want to build your own or find equivalent of HP461A if you are really serious looking into uV range.

in my design I got final 3.3v output of about 25 mv p-p ripple which is similar to another cheap design, which frustrated me since I wanted to do better... to reach <10 mv p-p. the 5v rail is worse, it is +30 mv p-p with lots of noise rather than ripple.

weird thing is that the other cheaper design showed similar behavior of 5v rail being noisier while 3.3v rail just ripple.
the PSU is for Dreamcast and the main power is for 3.3v rail (2.5~3 amps) while 5v rail not so much (maybe < 0.5 amp).

what do you suggest for routing and other optimizations?
i'm also learning and its hard to see whats on your pcb... i may give you useless advice anyway, so imho its not worth it to act like clever guy. imho you have to work yourself based on advices you received so far.. but i wonder why you want to still fight if its like an impossible battle? its like large promising market for Dreamcast PSU? many people in your place play Dreamcast? that you have to nail down other competitors in market? how about i give you advice, stop playing Dreamcast? ;D or does it need so low noise to work properly? i say thats a bad design for game console. or is it only yourself that want to challenge yourself? 30mVpp for smps is good output already imho. ymmv cheers.
« Last Edit: November 14, 2022, 09:03:04 am by Mechatrommer »
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Offline VEGETATopic starter

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Re: My PSU design ripple and noise with picture measurements
« Reply #188 on: November 14, 2022, 09:05:36 am »
Quote
yes thats your best at cheapest cost and easiest quick way.

I will try to use it soon and write feedback here.

Quote
'm also learning and its hard to see whats on your pcb... i may give you useless advice anyway, so imho its not worth it to act like clever guy. imho you have to work yourself based on advices you received so far.. but i wonder why you want to still fight if its like an impossible battle? its like large promising market for Dreamcast PSU? many people in your place play Dreamcast? that you have to nail down other competitors in market? how about i give you advice, stop playing Dreamcast? ;D or does it need so low noise to work properly? i say thats a bad design for game console. or is it only yourself that want to challenge yourself? 30mVpp for smps is good output already imho. ymmv cheers.

I am into retro gaming and it has nice community of people. yes, 30mv is fantastic but I still want to do better. the market for alternative PSUs exist but I wanted to make one that beats the others... if so, people will buy it for sure. Plus, the challenging thing you spoke about.

the lower the noise the better for retro consoles since it is all about analog video which gets affected by noise... 30mv or so is not bad really but as i said, i wanted better.

actually, all i wanted is to have better noise figure than others. that is all. later on i will create a mains powered psu to act as full replacement of the original psu... this will be based on this design but have something like meanwell ac-dc module as input.

i am fine with your advise since i am not an expert. i have done several revisions already but i cannot beat the 20-30 mv limit!

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Re: My PSU design ripple and noise with picture measurements
« Reply #189 on: November 14, 2022, 10:54:51 pm »
Hello,

I have used the spring and isolated the scope and stuff from other mains chargers as much as possible, here are the images: https://slow.pics/c/0H7FqG0j

all images are for my design except for when labelled "competitor".

any more images at certain time bases you need me to take?

^
All this for the newer design using TPS54394 dual buck.

However, as you know, I started this project using TPS62913 low noise buck regulator, I have dug it out and tested it as well... here are the pics for it + schematic attached: https://slow.pics/c/gQsPrODG  (layout picture available too, 3.3v rail is the first pin from the left of that 6-pin connector).

I switched from that IC due to price + it is almost always out of stock.

we used DLW5BTM501SQ2L common-mode choke, then we wanted to search for one which is better at attenuating 20-50 mhz noise... then i found PA4339.132NLT but I never used it in that "older" design due to out of stock IC but rather in the new design.


weirdly enough, the 5v rail of the older design is very clean, much better than newer design. but both suffer from 3.3v...

how do you think i can improve the new design taking all these stuff into consideration?

Offline jonpaul

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Re: My PSU design ripple and noise with picture measurements
« Reply #190 on: November 14, 2022, 11:51:20 pm »
bonjour à tous

Seems a classic case of poor measurement and probing technique

Suggest use BNC >>RG174/U coax, >> 450 Ohm series R make Zo probe with very short shield to plane loop. Dump the Chinese clone probes.

Check à good text on high frequency PCB layout and SMPS design and theory.

Do not depend on the TI application notés as gospel

Just the ramblings of an old retired EE

j
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Offline T3sl4co1l

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Re: My PSU design ripple and noise with picture measurements
« Reply #191 on: November 15, 2022, 05:23:00 am »
Take a picture of how and where you're probing.

Take waveforms at, at most, 5µs/div.  Zoom in during the load pulses.  I don't care what the load is doing on the order of 100s of Hz.  Your power supply should be (and is!) at least good enough not to have the least care what's going on at such boring frequencies!

Preferably, replace the Dreamcast with an actual load resistor, so you aren't seeing those damn load cycles as it's running.  What is it running, anyway?  Home screen?  Is a game loaded?  Is it rendering a lot or just a little?  Who knows.  The load is probably inconsistent and not reproducible.  Get it out of the lab!

Build your own step load generator to do that in a better controlled fashion.

Or, if this is actually what you are concerned with -- low frequency or DC response of the supply, not the filtering you've been concerned with for the last, this thread -- then realize that that is where you must focus your attention, (almost) no amount of capacitors will affect this aspect of the response!

Label your figures properly:
"3.3v competitor with spring" -- with spring where? How is it wired, where is it probed? Who is the competitor, how did they lay out their circuit, what other relevant points should I draw from this, etc.?
"both channels loose with spring math" -- loose how?  Floating in space?  Are the two probes' springs tied together or loose (open) as well?  What math? I don't see a function anywhere on screen!
"both channels with springs-ch1 for 3.3v and ch2 on ground" -- with math I guess, but again, what function?  Add?  Subtract?  ch2 is ground but how?  Is there significance to the distance or direction between probe and spring contacts, how could I know?

Mind, I enunciate these comments not to offend, but to emphasize and reiterate the importance of clarity, precision, and thinking critically about what you are doing, what you are saying.  Think about what someone else may read your comments as -- or what they won't know (because it's been omitted), that they should!

Tim
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Offline Mechatrommer

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Re: My PSU design ripple and noise with picture measurements
« Reply #192 on: November 15, 2022, 05:57:55 am »
If the 100hz is due to digital load its subjected to, then you have finite (non zero) impedance output psu... if its under dummy or passive resistor load i'll check for gnd loop/common mode error in probing. Gnd spring must be near power output, and then put probe tip on the same gnd spot where your spring lands, if you can still read the boring 100hz then you have gnd loop/common mode error in probing, else i think you have heavy current flow switching somewhere. In my psu i got 0.5Vpp after bypassing many high impedance nodes, it was 5Vpp spikes before! The loop controller went heywire.. and then i changed to significantly larger inductor for smps than whats i installed earlier ie recommended by 34063 app, then spikes went down to 60mVpp, it was current ripple! thats what my critical thinking tells me. The easiest imho is to sim the inductor switching and look at current ripple, not easy to do on real pcb..
« Last Edit: November 15, 2022, 06:00:03 am by Mechatrommer »
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Re: My PSU design ripple and noise with picture measurements
« Reply #193 on: November 15, 2022, 06:19:11 am »
Quote
Take a picture of how and where you're probing.

I will take those picture tonight. but i was probing the 6-pin connector with a spring grounded probe, not alligator ground. so path is very short.

Quote
Take waveforms at, at most, 5µs/div.  Zoom in during the load pulses.

so, time base in the nano seconds to 10us is the range you want? ok.

Quote
Preferably, replace the Dreamcast with an actual load resistor, so you aren't seeing those damn load cycles as it's running.

I wait until it loads the main screen or main screen of a game, then took those measurements so they are consistent. I have some load resistors (50W) but since the final application is DC I thought using it directly is better.

Quote
Build your own step load generator to do that in a better controlled fashion.

I want to buy some more advanced gear such as electronic load and so on in the future. However, as mentioned, right now the application of running this PSU on DC is what I want.

Quote
"3.3v competitor with spring" -- with spring where? How is it wired, where is it probed? Who is the competitor, how did they lay out their circuit, what other relevant points should I draw from this, etc.?

with spring = spring grounded not alligator clip ground. probed the 3.3v or 5v (depends on label) and gnd pins of the 6-pin connector. 3.3v pin is pin 1 from the left, 5v is pin 2, pin3 to pin5 are ground, pin 6 is 12v.
competitor is this.
12v power brick used with all is this.


Quote
"both channels loose with spring math" -- loose how?  Floating in space?  Are the two probes' springs tied together or loose (open) as well?  What math? I don't see a function anywhere on screen!

loose means they are not connected to anything, just on the bench and not connected to each other. math is channel 1 - channel 2.

Quote
"both channels with springs-ch1 for 3.3v and ch2 on ground" -- with math I guess, but again, what function?  Add?  Subtract?  ch2 is ground but how?  Is there significance to the distance or direction between probe and spring contacts, how could I know?

math here is channel 1 - channel 2.

channel 2 probe to ground and ground to ground via spring ground. so this is a differential measurement. all of this is probing the 6-pin connector. shortest ever distance between all those measurement points.


Quote
Or, if this is actually what you are concerned with -- low frequency or DC response of the supply, not the filtering you've been concerned with for the last, this thread -- then realize that that is where you must focus your attention, (almost) no amount of capacitors will affect this aspect of the response!

I told you my main goal for this device, it is to have the total noise and ripple figure to be < 10 mv p-p.

taking pictures of each frequency is fine by me too since it may help reduce the ripple.

so judging by these figures, how do you analyze what type of filtering required? I mean, it is obvious that adding bulk caps does not work as I tried putting some 220, 1000, etc elec. caps at the final load pins (6-pin connector) for 3.3v but had no effect. I also tried adding another 22uF ceramic but also didn't help.

so this leaves us with what conclusion?

I mean that ripple is about 50-60 hz or so... I have put CMC filter according to our mutual decision back in the mid of this thread. shouldn't bulk elec. cap reduce such low frequency ripple?

I do have another power brick but it is noisier, also a DIY bench switch mode psu that I built myself as other alternatives. the final product must be used with a 12v power brick so I picked the current one I linked above since it is better than the crappy noisy one. anyone who uses such a device will have a similar brick.

the point of CMC and input filters is to eliminate the ripple and noise generated by 12v power bricks as much as possible to have clean input to the switcher. however, as mentioned previously, the 33uH inductor and the following ferrites have increased amount of noise!

I made 2 units assembled of this design, i can for testing purposes, remove the 33uH inductor and the following input beads and just use the input bulk caps as main filtering caps, then see how it affects the overall system. but i am interested to know why this happened... especially that 33uH supposed to filter low frequency ripple.

what do you suggest?

best regards and always thanks for helping.

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Re: My PSU design ripple and noise with picture measurements
« Reply #194 on: November 15, 2022, 07:17:46 am »
If the 100hz is due to digital load its subjected to, then you have finite (non zero) impedance output psu... if its under dummy or passive resistor load i'll check for gnd loop/common mode error in probing. Gnd spring must be near power output, and then put probe tip on the same gnd spot where your spring lands, if you can still read the boring 100hz then you have gnd loop/common mode error in probing, else i think you have heavy current flow switching somewhere. In my psu i got 0.5Vpp after bypassing many high impedance nodes, it was 5Vpp spikes before! The loop controller went heywire.. and then i changed to significantly larger inductor for smps than whats i installed earlier ie recommended by 34063 app, then spikes went down to 60mVpp, it was current ripple! thats what my critical thinking tells me. The easiest imho is to sim the inductor switching and look at current ripple, not easy to do on real pcb..

well, I also suspect it is due to high current ripple switching but I am already using 4.7uH inductor which is on the high side + using 7x 10uF ceramics X7R which are also the maximum.

I started to suspect that choosing Chinese inductor + ceramic caps can be the issue due to, well, being not so good.

datasheet says this:

Quote
For the above design example, the calculated peak current is 3.46 A and the calculated RMS current is 3.01 A
for VO1. The inductor used is a TDK CLF7045-2R2N with a rated current of 5.5A based on the inductance
change and of 4.3A based on the temperature rise.
The capacitor value and ESR determines the amount of output voltage ripple. The TPS54394 is intended for use
with ceramic or other low ESR capacitors. The recommended value range is from 20µF to 68µF. Use Equation 7
to determine the required RMS current rating for the output capacitor(s).
(7)
For this design two TDK C3216X5R0J226M 22µF output capacitors are used. The typical ESR is 2 mΩ each.
The calculated RMS current is 0.19A and each output capacitor is rated for 4A.

my inductor is: https://www.lcsc.com/product-detail/Inductors-SMD_PSA-Prosperity-Dielectrics-MCS0630-4R7MN2_C385253.html

it has dc resistance of 37 to 40 mOhms, rated current is 5.5 amps which is way more than needed, saturation current is about 7 amps. and it is 4.7uH.
their suggested

datasheet inductor is CLF7045-2R2N -> 14 mOhm, 5.5 amps, 2.2uH.
evaluation board inductor is SPM6530T-2R2M -> 19 mOhm resistance, 8.4 amps. but this one is 2.2uH.

one thing to notice is their inductors are of lower dc resistance. my initial thoughts were that this can cause more heat. but can this really affect ripple performance?


my caps are CL31B106KAHNNNE -> 10uF X7R, ESR shown here. lowest is about 4mOhms at <1Mhz, at 700 khz it is about 4 mOhms... graph is just a picture, you can't check the actual data.

datasheet caps are C3216X5R0J226M which datasheet says 2mOhm ESR. at product page and datasheet I couldn't find such info. there is though a graph showing ESR, lowest is about 3.16mOhms at 525khz. for this 700 khz switcher it would be 3.3 mohms,

evaluation board caps are GRM31CR70J226KE19 having about 3mOhms at 700 khz.

hmm not so far away but still 1 mohm difference... is it worth it to get higher quality caps + inductors to enhance ripple noise performance? then other cheaper caps can be used in 2nd stage filtering + input filtering.




Offline Mechatrommer

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Re: My PSU design ripple and noise with picture measurements
« Reply #195 on: November 15, 2022, 09:08:13 am »
Yeah order from digikey dont buy from china, punch in the spec and you will get legit stock. in the end you'll have better performing but more expensive product :palm: why do you care about brand?  Inductor is an inductance you can even make your own.. your 1mVpp speced converter ic will take care of volt drop in control loop due to mOhm resistance,