Author Topic: My PSU design ripple and noise with picture measurements  (Read 46829 times)

0 Members and 1 Guest are viewing this topic.

Offline T3sl4co1l

  • Super Contributor
  • ***
  • Posts: 22436
  • Country: us
  • Expert, Analog Electronics, PCB Layout, EMC
    • Seven Transistor Labs
Re: My PSU design ripple and noise with picture measurements
« Reply #50 on: September 09, 2021, 09:45:36 pm »
Can you show top copper with pours enabled?

You'll have a heck of a time soldering FL1, best check those pads.

Tim
Seven Transistor Labs, LLC
Electronic design, from concept to prototype.
Bringing a project to life?  Send me a message!
 

Offline VEGETATopic starter

  • Super Contributor
  • ***
  • Posts: 2027
  • Country: jo
  • I am the cult of personality
    • Thundertronics
Re: My PSU design ripple and noise with picture measurements
« Reply #51 on: September 10, 2021, 10:33:05 am »
Can you show top copper with pours enabled?

You'll have a heck of a time soldering FL1, best check those pads.

Tim

they are in description.

it will be smt assembled not hand soldered.

do you think this will eliminate most or all cm noise?

Offline T3sl4co1l

  • Super Contributor
  • ***
  • Posts: 22436
  • Country: us
  • Expert, Analog Electronics, PCB Layout, EMC
    • Seven Transistor Labs
Re: My PSU design ripple and noise with picture measurements
« Reply #52 on: September 10, 2021, 01:14:24 pm »
Hmm, still can't figure it out, like why does the top copper not seem to pour over the bottom side traces?  They're both green, it's very ambiguous.

Tim
Seven Transistor Labs, LLC
Electronic design, from concept to prototype.
Bringing a project to life?  Send me a message!
 

Offline VEGETATopic starter

  • Super Contributor
  • ***
  • Posts: 2027
  • Country: jo
  • I am the cult of personality
    • Thundertronics
Re: My PSU design ripple and noise with picture measurements
« Reply #53 on: September 10, 2021, 01:32:25 pm »
Hmm, still can't figure it out, like why does the top copper not seem to pour over the bottom side traces?  They're both green, it's very ambiguous.

Tim

What connector exactly?

I chose "solid" for copper pours, so all pads will blend in with the copper pour without thermal relief stuff. top side is red while bottom side is green.

I can make more photos if you want but kindly mention what exactly is the thing you want to see.

Also, will this solve the noise problem? the layout is good now? I am interested in those more.

Offline T3sl4co1l

  • Super Contributor
  • ***
  • Posts: 22436
  • Country: us
  • Expert, Analog Electronics, PCB Layout, EMC
    • Seven Transistor Labs
Re: My PSU design ripple and noise with picture measurements
« Reply #54 on: September 10, 2021, 02:01:44 pm »
I mean, like if I zoom in over here, the via seems to be completely surrounded by black.  Which is obviously absurd, why would it dead end?

Ohhhh, zooming in, and cranking the shit out of the brightness -- I can see what's going on.  The connecting trace has RGB 33,0,0 against a background of black 0,0,0 (original levels).  Your eyes must be much better than mine (or your monitor is, or, it's a whole lot worse..!), to actually be doing work like that?

Tim
Seven Transistor Labs, LLC
Electronic design, from concept to prototype.
Bringing a project to life?  Send me a message!
 

Offline T3sl4co1l

  • Super Contributor
  • ***
  • Posts: 22436
  • Country: us
  • Expert, Analog Electronics, PCB Layout, EMC
    • Seven Transistor Labs
Re: My PSU design ripple and noise with picture measurements
« Reply #55 on: September 10, 2021, 02:02:50 pm »
Aha, amping up the red channel, and narrowing green a bit, gets something that looks a lot like old school Ultiboard. ;D

Why can't they use these as default settings though? :-//

Tim
Seven Transistor Labs, LLC
Electronic design, from concept to prototype.
Bringing a project to life?  Send me a message!
 

Offline T3sl4co1l

  • Super Contributor
  • ***
  • Posts: 22436
  • Country: us
  • Expert, Analog Electronics, PCB Layout, EMC
    • Seven Transistor Labs
Re: My PSU design ripple and noise with picture measurements
« Reply #56 on: September 10, 2021, 02:17:16 pm »
So here's what I'd like to change:
- Move the traces to the blue paths.  This keeps ground solid under the regulators.
- Add vias where shown (blue circles).  This keeps top and bottom ground solid, stitching around traces.

Note that the inductor is not a high-current switching path, it's fine to run traces under there, within reason.  No problem from cutting the ground (i.e. the negative space created by pouring around a trace).  And this trace isn't sensitive to noise.

- Remove a couple caps (blue X's) and add a series inductor (purple).  This filters the 12V passthru/out.

All the filters are clustered around the bottom so the output connector should be nice and quiet.  The input connector is across the board so can pick up some switching noise, but at least the switching currents should be tightly contained, and are surrounded by lots of ground copper, keeping the voltage drop small.  And there's a CMC, which helps.

The overall number of capacitors is... rather obnoxious, but they don't hurt anything being there, they can always be depopulated on assembly.  Do check for compensation / stability (load step test).

The layout could be smaller, I suppose, for example if less space were taken up where 12V is routed around one regulator to the other; they could just be chained on the same trace, no problem.

Tim
Seven Transistor Labs, LLC
Electronic design, from concept to prototype.
Bringing a project to life?  Send me a message!
 

Offline VEGETATopic starter

  • Super Contributor
  • ***
  • Posts: 2027
  • Country: jo
  • I am the cult of personality
    • Thundertronics
Re: My PSU design ripple and noise with picture measurements
« Reply #57 on: September 10, 2021, 03:10:34 pm »
Hello,

- I re-arranged those traces to make better grounding. I should not get feedback circuit under the noisy inductor, therefore I made those routes and re-routes. However, the other resistor is for power good function which doesn't care about noise but still managed to get it without going under the L.

- I didn't remove the 12v filter caps since I don't know the inductor value and therefore I could use 4.7uH which I used here. Plus I already put 4.7uH one as seen in schematic and layout (upper right). Do you mean I remove 22uF+47uF caps and put a 4.7uH instead just for output connector? since they won't be feeding the switchers.

- added more vias in different places.

number of output caps for each switcher stages are correct. I need total capacitance to be less than 200uF, here it is about 201uF or so... 1206 package is good for that despite they are putting 0805 in datasheets but that is mainly because they were interested in showing how this part actually reduces space. I have enough space therefore I can put such caps. They only recommended ceramic caps but I added an electrolytic 47u at the end.

It is possible to eliminate all 47uF elec. caps and just use 22uF ceramics since 1206 is kinda good with 3.3v and 5v. but 47u ensures more capacitance rather than get reduced by dc bias. plus, 12v is very harsh on ceramics due to dc bias.

from this and your opinion, how much noise\ripple can we get as a total figure? I really want it to be so low even if it is not fully needed to be so. perfection is always desired xD. Previous comments suggested that CMC is the key to reduce all this which is why I added it + the layout note about vias. I hope now it is done.

problem is I can't order this again due to high cost of assembly for mere 5 boards. JLCPCB doesn't have all the parts either, the TI switcher is impossible to hand solder! I am trying to have a solution which ensures very little cost to try at least 1 board fully assembled.

Offline T3sl4co1l

  • Super Contributor
  • ***
  • Posts: 22436
  • Country: us
  • Expert, Analog Electronics, PCB Layout, EMC
    • Seven Transistor Labs
Re: My PSU design ripple and noise with picture measurements
« Reply #58 on: September 10, 2021, 09:18:05 pm »
Yes, 4.7uH is fine.  You're not filtering the output from the input, you're filtering it from the switchers, which throw quite a lot of noise upstream.  It would likely be fine also to bypass it all, loop the raw input (after the CMC) around the side, down to the connector.

Tim
Seven Transistor Labs, LLC
Electronic design, from concept to prototype.
Bringing a project to life?  Send me a message!
 

Offline VEGETATopic starter

  • Super Contributor
  • ***
  • Posts: 2027
  • Country: jo
  • I am the cult of personality
    • Thundertronics
Re: My PSU design ripple and noise with picture measurements
« Reply #59 on: September 10, 2021, 10:19:34 pm »
Quote
It would likely be fine also to bypass it all, loop the raw input (after the CMC) around the side, down to the connector.

meaning what exactly? putting ceramic caps around CMC?

I will put 4.7uH instead of those 2 caps next.

Offline T3sl4co1l

  • Super Contributor
  • ***
  • Posts: 22436
  • Country: us
  • Expert, Analog Electronics, PCB Layout, EMC
    • Seven Transistor Labs
Re: My PSU design ripple and noise with picture measurements
« Reply #60 on: September 10, 2021, 11:00:55 pm »
Bypass in the plain meaning, run the trace around the right edge, ignoring the internal 12V pour.

Tim
Seven Transistor Labs, LLC
Electronic design, from concept to prototype.
Bringing a project to life?  Send me a message!
 

Offline VEGETATopic starter

  • Super Contributor
  • ***
  • Posts: 2027
  • Country: jo
  • I am the cult of personality
    • Thundertronics
Re: My PSU design ripple and noise with picture measurements
« Reply #61 on: September 11, 2021, 11:45:23 am »
Bypass in the plain meaning, run the trace around the right edge, ignoring the internal 12V pour.

Tim

you mean give it a separate path? this way it won't benefit from the huge 1000uF capacitor.

Offline T3sl4co1l

  • Super Contributor
  • ***
  • Posts: 22436
  • Country: us
  • Expert, Analog Electronics, PCB Layout, EMC
    • Seven Transistor Labs
Re: My PSU design ripple and noise with picture measurements
« Reply #62 on: September 11, 2021, 03:01:11 pm »
Who cares, don't need it anyway. Or put it on the other side of the 4.7uH.

Tim
Seven Transistor Labs, LLC
Electronic design, from concept to prototype.
Bringing a project to life?  Send me a message!
 

Offline VEGETATopic starter

  • Super Contributor
  • ***
  • Posts: 2027
  • Country: jo
  • I am the cult of personality
    • Thundertronics
Re: My PSU design ripple and noise with picture measurements
« Reply #63 on: September 12, 2021, 06:06:58 pm »
Hello,

I have done it.

- re-arranged 12v stuff.
- added another 4.7uH inductor, now has 2 separate paths of 12v... one for output connector, one for switchers. Both stages supplied by 1000uF+47uF capacitors.
- each 12v stage has 22uF ceramic + 47uF elec. cap.
- layout is done where the 2 inductors are on the side.

is it good now? does it need anything else?

what noise\ripple expected now?

regards!

Offline T3sl4co1l

  • Super Contributor
  • ***
  • Posts: 22436
  • Country: us
  • Expert, Analog Electronics, PCB Layout, EMC
    • Seven Transistor Labs
Re: My PSU design ripple and noise with picture measurements
« Reply #64 on: September 13, 2021, 03:49:47 am »
Nice!

Hm, I would add one via:

That should do it.

Tim
Seven Transistor Labs, LLC
Electronic design, from concept to prototype.
Bringing a project to life?  Send me a message!
 

Offline VEGETATopic starter

  • Super Contributor
  • ***
  • Posts: 2027
  • Country: jo
  • I am the cult of personality
    • Thundertronics
Re: My PSU design ripple and noise with picture measurements
« Reply #65 on: September 13, 2021, 05:24:25 am »
Nice?! you should say "marvelous" hhhhh xD

I will add that via today when I get back.

First time for me to know that adding vias like this is vital in PCB design. Also, that doing ground pour on both layers is the best way to go. However, in 4 layers stack, I guess I should have signal-gnd-gnd-signal stack right? since the 3rd layer can be a power layer but sometimes I would have multiple power rails which makes it difficult to put them all on one power plain, therefore making it gnd is better right? I could just route power on signal layers.

I understand that vias are short path to gnd which makes it easy for current to go to ground instead of travelling long distance, therefore noise will be significantly reduced overall. is that correct?

what is more to learn about this? what more improvement I can do? is the CMC part suitable and how to choose a suitable one?

most importantly, do you think I can achieve < 1mV total noise\ripple this way? maybe at least < 5mV p-p? how much exactly?

Offline T3sl4co1l

  • Super Contributor
  • ***
  • Posts: 22436
  • Country: us
  • Expert, Analog Electronics, PCB Layout, EMC
    • Seven Transistor Labs
Re: My PSU design ripple and noise with picture measurements
« Reply #66 on: September 13, 2021, 06:18:42 am »
Oh, one more thing but it's unrelated to electrical performance per se.  With all that copper, and via stitching, and direct-pour pads, you may find soldering is quite difficult.  Especially on those undersized pads for the CMC.  Basically the whole board needs to reach soldering temp before anything will melt.  And the direct-pour pads have extra surface tension that tends to lift components, leading to tombstoning, particularly when the other pad just has one or two traces leading out of it.  (Tombstoning isn't much of a problem for 0805 and larger, but is a concern for smaller chips.)  If nothing else, you'll have a hell of a time doing any rework with a soldering iron; hope you have a hot air machine.

2-4 spokes (thermal relief) drops just enough thermal resistance to make soldering a little easier, while having essentially no electrical impact, and for thermal dissipation purposes (at regular component-self-heating power densities) has little effect as well.  (That is, because soldering is done with more heat, the temp drop is higher, so the spokes are helpful there, while also being mostly inconsequential in operation.)

5mV is probably in the right ballpark.  I'd have to do some calculations to give a better guess.

Note that we still have not resolved whether your power adapter in the first place is the source of noise, nor of what the spectrum looks like (just a forest of spikes, modulated at 50Hz).  If it is the adapter, the CMC will at least help a bit, but you may still not observe the noise floor of the board itself, if this is the case.

Tim
Seven Transistor Labs, LLC
Electronic design, from concept to prototype.
Bringing a project to life?  Send me a message!
 

Offline VEGETATopic starter

  • Super Contributor
  • ***
  • Posts: 2027
  • Country: jo
  • I am the cult of personality
    • Thundertronics
Re: My PSU design ripple and noise with picture measurements
« Reply #67 on: September 13, 2021, 06:30:38 am »
Oh, one more thing but it's unrelated to electrical performance per se.  With all that copper, and via stitching, and direct-pour pads, you may find soldering is quite difficult.  Especially on those undersized pads for the CMC.  Basically the whole board needs to reach soldering temp before anything will melt.  And the direct-pour pads have extra surface tension that tends to lift components, leading to tombstoning, particularly when the other pad just has one or two traces leading out of it.  (Tombstoning isn't much of a problem for 0805 and larger, but is a concern for smaller chips.)  If nothing else, you'll have a hell of a time doing any rework with a soldering iron; hope you have a hot air machine.

2-4 spokes (thermal relief) drops just enough thermal resistance to make soldering a little easier, while having essentially no electrical impact, and for thermal dissipation purposes (at regular component-self-heating power densities) has little effect as well.  (That is, because soldering is done with more heat, the temp drop is higher, so the spokes are helpful there, while also being mostly inconsequential in operation.)

5mV is probably in the right ballpark.  I'd have to do some calculations to give a better guess.

Note that we still have not resolved whether your power adapter in the first place is the source of noise, nor of what the spectrum looks like (just a forest of spikes, modulated at 50Hz).  If it is the adapter, the CMC will at least help a bit, but you may still not observe the noise floor of the board itself, if this is the case.

Tim

You mean choose "thermal relief" in Kicad instead of "solid" for ground pours? I can also make CMC pads bigger.

I won't be doing any rework stuff anyway, but adding thermal reliefs seems reasonable enough.

I hope I can get below 5mV if possible, how can you calculate that now?

there is nothing else besides the power adapter anyway. I used a reasonably-good one, I have worse. users might have better or worse too. the forest of spikes at 50 hz seems not good to me since this is not the switching frequency of the power adapter. therefore, we concluded here in this thread that it is CM noise. I think you can still see the ripple waves caused by the power adapter in the pictures.

Offline T3sl4co1l

  • Super Contributor
  • ***
  • Posts: 22436
  • Country: us
  • Expert, Analog Electronics, PCB Layout, EMC
    • Seven Transistor Labs
Re: My PSU design ripple and noise with picture measurements
« Reply #68 on: September 13, 2021, 08:08:49 am »
Yes, thermal relief.

Oh, and keep vias direct, thermals there just take up space.

Calculations require building a model, which will take several hours to do; I'm guessing you don't have the budget for me to do that, but if you like, references can be found for using simulators, and building EMI equivalent networks.  Which, without starting knowledge, it will take some, probably weeks to get up to speed -- well worth it if you're planning on making more supplies and stuff though.  Well... weeks, more like months including background material like how to setup and measure networks, RF port theory, CM/DM etc...

Tim
Seven Transistor Labs, LLC
Electronic design, from concept to prototype.
Bringing a project to life?  Send me a message!
 

Offline VEGETATopic starter

  • Super Contributor
  • ***
  • Posts: 2027
  • Country: jo
  • I am the cult of personality
    • Thundertronics
Re: My PSU design ripple and noise with picture measurements
« Reply #69 on: September 13, 2021, 06:09:25 pm »
Done. I had to re-arrange stuff around switchers when making thermal reliefs.

I may increase the pad sizes of CMC if it is necessary.

Offline BrianHG

  • Super Contributor
  • ***
  • Posts: 8283
  • Country: ca
    • LinkedIn
Re: My PSU design ripple and noise with picture measurements
« Reply #70 on: September 14, 2021, 04:48:07 am »
You have 1 trace which may be damaged by the mounting screw and the same thin trace right at the edge of the PCB. see photo for fix...
 

Offline VEGETATopic starter

  • Super Contributor
  • ***
  • Posts: 2027
  • Country: jo
  • I am the cult of personality
    • Thundertronics
Re: My PSU design ripple and noise with picture measurements
« Reply #71 on: September 14, 2021, 04:57:01 pm »
You have 1 trace which may be damaged by the mounting screw and the same thin trace right at the edge of the PCB. see photo for fix...

I fixed it, plus added some vias under inductors.

Offline T3sl4co1l

  • Super Contributor
  • ***
  • Posts: 22436
  • Country: us
  • Expert, Analog Electronics, PCB Layout, EMC
    • Seven Transistor Labs
Re: My PSU design ripple and noise with picture measurements
« Reply #72 on: September 14, 2021, 06:42:31 pm »
The reliefs seem pretty large, just 7 to 10 mils is enough expansion / clearance.  And similar for spoke/web width.

Which, huh, a few look super thick, like the uh, whatever the row of capacitors is above the middle regulator, I can't read the silk from here.  Looks like there's fat ass traces hidden by the polygon or something?  If those are required for connectivity / pouring, I'd shrink them, and align them with the spokes so you aren't creating extra or thickened ones.

Tim
Seven Transistor Labs, LLC
Electronic design, from concept to prototype.
Bringing a project to life?  Send me a message!
 

Offline VEGETATopic starter

  • Super Contributor
  • ***
  • Posts: 2027
  • Country: jo
  • I am the cult of personality
    • Thundertronics
Re: My PSU design ripple and noise with picture measurements
« Reply #73 on: September 14, 2021, 08:42:19 pm »
The reliefs seem pretty large, just 7 to 10 mils is enough expansion / clearance.  And similar for spoke/web width.

Which, huh, a few look super thick, like the uh, whatever the row of capacitors is above the middle regulator, I can't read the silk from here.  Looks like there's fat ass traces hidden by the polygon or something?  If those are required for connectivity / pouring, I'd shrink them, and align them with the spokes so you aren't creating extra or thickened ones.

Tim

kindly check attached images. first one is for ground pour settings so you can see and advise which ones to change, the 2nd one is for showing the traces (blue arrow, red arrow, black arrow) to see which ones you mean.

if you mean blue arrow, this trace size is 2 mm which is the biggest since it is the main power input for the regulators as you can see... came from 12v rail. Should I shrink it a bit, to be 1? since there was nothing around it I thought of making it big.

Offline T3sl4co1l

  • Super Contributor
  • ***
  • Posts: 22436
  • Country: us
  • Expert, Analog Electronics, PCB Layout, EMC
    • Seven Transistor Labs
Re: My PSU design ripple and noise with picture measurements
« Reply #74 on: September 15, 2021, 09:20:27 am »
Yes the traces are too fat in places, they can be necked down locally, or for just an ampere or two they don't need to be very wide at all, 0.5 to 1mm.  And you can get 2oz copper for extra handling.

Yeah thermal relief and clearance, 0.254 mm will do.

Tim
Seven Transistor Labs, LLC
Electronic design, from concept to prototype.
Bringing a project to life?  Send me a message!
 


Share me

Digg  Facebook  SlashDot  Delicious  Technorati  Twitter  Google  Yahoo
Smf