here are the ferrite beads: https://www.fair-rite.com/product/sm-beads-differential-mode-2773037447/
the reason to include them was to do some filtering of noise, this particular one can do for lower frequencies. putting inductors will cause drop voltage, and I don't know what value inductor to use. thus, thought that FB was a better choice since its resistance is like 1.2 mOhm.
You can get inductors like that you know...
Look at the impedance curve. See the 1A curve. See how it's so depressed? How much filtering value do you think you're getting in that condition?
Better yet, don't think -- calculate! What is the attenuation for such impedance at 1A and 1MHz? 10MHz? (Bonus points: include capacitor ESR and ESL too!)
(That we should be so fortunate as to be able to model and predict everything we do in EE. Not always easily enough to be worth doing, but in principle at least. But this case happens to be one of the easiest to model.)
where exactly? at which stage?
Yes. (Inclusive-or. All of them, most likely.)
if at LDO stage which has 5x 22u ceramics... is it ok to add another 22u ceramic in series with say 100R resistor as a damper instead of an elec. cap? or better yet 1uF cap with 100R or so? since I do have 1uF in design and it is small and won't take space.
What the heck will 100R do?
...And how would one figure it out?
R = sqrt(L/C), for C being total capacitance (may be the series equivalent of caps on either side of the inductor in question), and L the inductor between it. Cbulk >= 3C.
You propose R = 100 ohm and Cbulk = C/5. Even at best, with L(FB) being, let's see, about 40 ohms at 1MHz (zero DC bias) or ballpark 6.4uH, and assuming the capacitors don't drop under bias (they certainly will -- check the characteristic sheet), you'll have 5*22 = 110uF, or Zo = sqrt(6.4/110) = 17 ohms. 100R will reduce the ringing moderately, but won't bring it down to zero (well damped, or overdamped).
(Normally, this kind of connection does not give an overdamped condition; much more Cbulk is needed to get there. Somewhere around slightly underdamped to critically damped will do fine, anyway.)
Inverting the capacitor counts is more likely to be helpful. Say just one or two 22uF in parallel, then an R+C using 3-4 in parallel, plus whatever resistance is appropriate.
The fact that Zo is so high, has substantial implications for the load step response. This impedance has physical meaning. It represents the peak change in voltage, from a step change in load current. If you want 10% regulation at 3.3V, for a step change of say the full 2 or 3A load (whatever it was?), that's 0.33V/3A = 0.1 ohm. Evidently for C = 110uF you need L < 1.1uH. But for C being smaller as described above, L will be smaller still.
You can measure all of these quantities with a suitable setup.
I don't know how many ways I can emphasize this, by the way.
You can, physically, practically, in a couple of minutes, set up a test to measure all of these parameters. Impedance, time constant, step response, output DC resistance.
You can do it with an automatic pulse generator, like a 555 into a MOSFET and resistor.
You can do it with a resistor and a wire in your goddamn hand -- you have a DSO more than capable of capturing single events. You can touch a wire, get the single capture, and inspect the waveform at your leisure! Very handy indeed.
Anyway.
To do that RC with fewer components, an electrolytic will have about the right ESR, or can be chosen nearby at least. So, 0.1 ohm ESR, 0.1 ohm Zo, and the output doesn't do any ringing, no nasty step response shenanigans, nice and solid.
Matter of fact, go ahead and do the all-ceramic thing. Set yourself up for another mess of waveforms. Do the tests. See them ring. See the steps.
Then glom on a big fatty sloppy ESR-y electrolytic.
See it all go "thud".
See it fix all the ringing.
Tweak some other component values. Goob in a smaller inductor.
Then see what the step response does.
You can do all of this so so easily.
I don't know what I possibly have to tell you to get you to do this.
It's so painfully easy and pleasant to do.
You just have to be willing to grab a few damn resistors and sit down at the scope.
And zoom your scope in once in a while.
What time constant is this all happening at, by the way?
We know this, precisely, as well!
The LC time constant is pi sqrt(L C)/2. The RC or L/R time constant is, well, exactly those. Any of those pairs of variables will get you something of interest.
elec cap will be huge capacitance value which will affect the stability of the switcher, or so TI recommended. I am already exceeding maximum allowed capacitance of 68u.
You don't seem to be too concerned about that given the other poster suggesting you exceed the recommended inductance value as well...
Add a bypass resistor (optional 0 ohm jumper) to try it without the LDOs first.
at the output of switchers? I can add a load resistor, say 1k ohm to ground.
if 0 resistor is used, then it will be like a connecting bridge between switchers output and LDO stage. is this what you want?
Bypass, as in, to short from SMPS output to LDO output, with LDO removed (DNP = do not place). To pass it by. By-pass it, as it were.
Or you can jumper over it with a stupid bodge wire, that's fine too, but as long as you're going to the trouble of making another board, why not make it easy on yourself?
On another point, do you find this layout good? knowing that i am simply adding footprints and so on, not a real design yet but just a rough layout.
The placement should be a significant improvement. I would not bother with the LDOs at all.
Mind, it's still not clear how much of any of this actually matters, because even just your waveforms and testing are woefully insufficient. Some combination of these mechanisms (filtering, LDO, CM) will have effect at
some point, but how much of one kind of filtering you need to employ before the other comes to dominate, isn't clear.
Somewhat aside, the LDO idea itself is bothersome:
So many people say "just add postreg to clean it up!!", completely ignorant of:
- LDOs have shite PSRR in general, particularly at modest to high frequencies (>10kHz), and at low Vin-Vout (with some standout exceptions);
- A better differential filter and higher Fsw is cheaper and more efficient;
- An LDO does fuck all for common mode noise, which can't be helped by ANY amount of differential filtering. CM is dominated by layout alone, and some use of CMC, but also more layout.
I think the idea of a postreg mainly persists (i.e.
it meets the definition of a meme) because:
1. It's just complicated enough for one to feel proud of building/designing, while still being easy enough to succeed;
2. It sounds good / has a believable function (but as mentioned above, it need not actually succeed at that goal!!),
3. People see a lot of others doing it so it must be good right??!?
3a. ...Nevermind *who* they see doing it. Or not doing it:
Few professionals use postregs (read: very often, or at all). And for the occasions that that additional filtering really is well and truly necessary, and where burning that little voltage overhead really is worthwhile (e.g. smaller than the DM filter components), not just any damn LDO will be used, but a type with especially good PSRR (some are in fact available, targeting RF equipment for example), or a discrete circuit such as a "capacitor follower" (taking advantage of BJT characteristics to get exceptional performance).
4. And most especially of all: nevermind if they know they need it in the first place -- or can verify (or have any way to verify!) that it's doing ANY of the claims set out in whatever they saw that inspired them to build it!
Few professionals likewise use them, because there just isn't any damn point to it. I regularly measure single digit mV output ripple on point-of-load converters, running typical things, you know, an MCU, a few interfaces and peripherals (amplifiers, RS-485 transceivers, etc., you know, the usual add-on junk).
For something like your load with large and frequent fluctuations (variable CPU and GPU activity during a frame, and between frames), 10s of mV would seem normal, and perfectly acceptable. I have no idea what that system actually specifies (you'd have to see their internal design documents, or at least the data of everything that's running from those direct rails), but I would be shocked if it even cares about 100s of mV. Perhaps some random glitches would start to occur at that level, who knows.
And then, anything less than that [some 10s of mV], it... simply doesn't matter. It's meaningless. It provides no performance or reliability improvement. It's an internal connection (at least, I assume this connector and cable is short and internal?), it likely doesn't affect EMC. (Emissions up the power-input cable may be relevant, which will be affected by emissions on the output connector, by the principle of reaction ("..equal and opposite force.."). But no further than that.)
As for just getting it low for, shall we say, academic purposes -- well, now we're measuring something. So get to measuring. Do the step load tests, see the transient response. Zoom in and see the switching ripple. Zoom in further and see the CM noise.
Can even set up a LISN and measure emissions. Wire up a ground plane with a few bias tees dotted around, wire up the connectors, and see what noise is present on each one. Can be used as an introduction to RF theory and EMC testing too. Lots of academic value we can explore around a humble power supply.
Tim
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