Author Topic: NAND flash with two chip-select  (Read 1664 times)

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Offline zphazeTopic starter

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NAND flash with two chip-select
« on: July 14, 2020, 09:17:00 pm »
Hi,

I want to use this NAND flash chip, which has a capacity of 64Gbit. *(datasheet http://pdf.datasheet.live/e35a5359/micron.com/MT29F64G08CBABBWP-12%3AB.pdf)
On the pinout, I have two chip enable PINs (CE#/CE2#) :


This chip has two dies inside the same package, but I technically only have one NAND_CE pin on my MCU (I don't have two).

I wonder if anybody being familiar with NAND interfacing knows if it's doable to tie both chip enable (CE) PINs with a logic gate, so that if one needs to be enabled, both will always be enabled at the same time.
Is the chip somewhat using the chip enable PIN as an "extra addressing bit" so that we cannot really enable both because the addressing will become confused (i.e. if both dies have the same 00h-FFh addresse ranges or something like that), or is it doable to have one PIN driving the two chip selects with logic glue.

Thanks!
 

Offline QuitButton

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Re: NAND flash with two chip-select
« Reply #1 on: July 14, 2020, 09:41:48 pm »
Page 24 of the datasheet shows them as being separate logical units, so its in effect 2 separate chips in one case. So your "extra addressing pin" view of how it works is what it says it does.

Or in other words,  you need to enable each LU individually.
 
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Offline thm_w

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Re: NAND flash with two chip-select
« Reply #2 on: July 14, 2020, 09:53:29 pm »
Its a distinct die so the memory addressing is going to be the same.
Maybe some sort of address decoding or using a general IO pin is possible? What processor are you using?

Quote
Asynchronous Enable/Standby
A chip enable (CE#) signal is used to enable or disable a target. When CE# is driven LOW, all of the signals for that target are enabled. With CE# LOW, the target can acceptcommands, addresses, and data I/O. There may be more than one target in a NAND Flash package. Each target is controlled by its own chip enable; the first target (Target 0)is controlled by CE#; the second target (if present) is controlled by CE2#, etc
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Offline David Hess

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Re: NAND flash with two chip-select
« Reply #3 on: July 15, 2020, 04:34:10 pm »
Is the chip somewhat using the chip enable PIN as an "extra addressing bit" so that we cannot really enable both because the addressing will become confused (i.e. if both dies have the same 00h-FFh addresse ranges or something like that), ...

That is effectively exactly what it is, an extra address bit which requires external decoding.
 

Offline QuitButton

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Re: NAND flash with two chip-select
« Reply #4 on: July 15, 2020, 07:25:39 pm »
Page 2 of the datasheet shows  different Classifications are available with different die numbers.  Is there one available in the size you want with a single die?
 


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