Author Topic: [Solved] NanoVNA says impedance of my 3200R resistor is 542R-1250X at 50 MHz  (Read 7977 times)

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Offline ogden

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Look, you are making comments like: "I suspect that you think that S21 thru calibration do not measure/calibrate Port2 impedance. Well, it does."

I have repeatedly explained the calibration options available for the port 2 calibration, but you say something like that.
Yes. You made such  impression. Especially when you said following: "3. 1 path 2 port calibration. I _think this should_ correct for everything and be almost as good as a Full 2 port cal, but requires a manual DUT reversal" when we talk about impedance measurements of symmetric components like resistor, capacitor, inductor. Also knowing that NanoVNA does SOLTI calibration, you believed that it is just scalar analyzer  :palm:. Whatever. As you promised to spread your wizdom, please stay tuned. Questions will follow. I will try to ask them one by one.

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"BTW components such as resistor & inductor (some other components as well) are "single port devices" that do not need to be rotated during impedance measurements."

Sarcastic much? They are only single port if measured in S11 shunt. The pdf which Brian (virtualparticles) wrote explains in detail that there are different methods. There are even pictures on the first page. Then there is a chart which helps us decide which method to use. It's gold.

You just don't appear to be interested in learning, all I am seeing from you is a desire to argue.
Here's question: how and why impedance measurements can be improved by rotating symmetric component (DUT), let's say resistor, on S11+S21 instruments like NanoVNA and/or 8753 + 85044 T/R test set? I am listening. Please no obscure :blah:, better explain it well. Yes, I am interested in learning and others may benefit as well.
« Last Edit: October 21, 2019, 06:41:53 am by ogden »
 

Offline bson

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Any time delay calibration error will show up as a phase deviation in S11 measurements, which will then become reactance when deriving the impedance.  For this reason, time delay must be measured using a reference load and derived from the phase measurement of the reference load/open to null it out.  For RF you need reference data for the load/open (the calibration load, not input load), but for 10-50MHz this shouldn't be necessary - but it's definitely necessary to properly null it. (Possibly the short also.)
« Last Edit: October 21, 2019, 04:30:01 pm by bson »
 

Offline hendorog

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Look, you are making comments like: "I suspect that you think that S21 thru calibration do not measure/calibrate Port2 impedance. Well, it does."

I have repeatedly explained the calibration options available for the port 2 calibration, but you say something like that.

Yes. You made such  impression. Especially when you said following: "3. 1 path 2 port calibration. I _think this should_ correct for everything and be almost as good as a Full 2 port cal, but requires a manual DUT reversal" when we talk about impedance measurements of symmetric components like resistor, capacitor, inductor. Also knowing that NanoVNA does SOLTI calibration, you believed that it is just scalar analyzer  :palm:. Whatever. As you promised to spread your wizdom, please stay tuned. Questions will follow. I will try to ask them one by one.


Your own :blah: isn't helping, and insulting me isn't helping either. You have only made general comments which are something like: 'nanovna can't do it because it has poor dynamic range', and then 'nanovna has everything which is needed' and then 'you think the nano can't measure phase'.

You are just as confusing to communicate with as I don't understand how you are jumping to these conclusions.

Firstly, let me say this: I agree that the nano can do these S11 and S21 measurements. I never said it couldn't. <-- Read this again.

The point I am making is that there are different levels of accuracy which can be achieved.

The measurement can be more accurate - or at least as accurate as possible - if we:
* Use the right fixture for the measurement <-- see Brians paper
* Do better fixture removal than just port delay only
* Use a better calibration algorithm.
* Limit the frequency range of the measurement

On the calibration algorithm, as I indicated I am not sure if the 1 path 2 port will turn out to be better than Enhanced Response.
But lets find out...

I will try to find a document describing it and will come back with a reference. Its implemented in scikit-rf I believe.
In the meantime here is something I found where the 8753 designer talks about it briefly:
https://community.keysight.com/thread/5003

Quote
The 8753C did have a one-path two-port cal, and it was used with the TR test set for the 8753C (85044?).  The process for calibration was to connect the DUT, hit trigger, the 8753 would prompt you to reverse the DUT, which you would do, then hit trigger again, and it would gather the both forward and reverse parameters and display all 4 s-parameters.  So, it was a real full 2 port measurement (just like the 8510, but I've never used one in that mode).

For "blesia", you must ALWAYS have a path from the 8753 source to the R-channel input.  You see, the source is phase locked to the synthesized receiver, but the receiver must have a bit of signal in it (-35 dBm Min), to allow the phase lock to work.  The 85044 T/R test set has a splitter inside to provide a reference signal, as well as a bridge for a reflectometer back to A.  For transmission the cable just goes straight to B.  You must use this test set for the one-path 2-port to work.

 

Offline ogden

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Put analysis of my conclusions away and let me learn. You did not answer my question about DUT such as resistor, manual reversal and how it improves impedance measurements. Note that I am asking you specific question, about reversal of DUT which is resistor. Hopefully I do not need to explain what is resistor and how it differs from fixture with resistor in it? [kidding]

In the meantime here is something I found where the 8753 designer talks about it briefly:
https://community.keysight.com/thread/5003
They talk about network analysis of two port devices such as filters amplifiers and so on. We talk about impedance analysis of symmetric components.
« Last Edit: October 21, 2019, 08:57:29 pm by ogden »
 

Offline hendorog

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Put analysis of my conclusions away and let me learn. You did not answer my question about DUT such as resistor, manual reversal and how it improves impedance measurements. Note that I am asking you specific question, about reversal of DUT which is resistor. Hopefully I do not need to explain what is resistor and how it differs from fixture with resistor in it? [kidding]

In the meantime here is something I found where the 8753 designer talks about it briefly:
https://community.keysight.com/thread/5003
They talk about network analysis of two port devices such as filters amplifiers and so on. We talk about impedance analysis of symmetric components.

No problem, same applies for me.

The DUT reversal is _only_ related to the one path two port calibration. This is not a common thing anymore as everyone has 2 port analysers.

A symmetric component is a special case of a two port component. In the case of a perfectly symmetric component and fixture then I agree with you - you don't need to reverse the DUT. That is an optimisation of the general case of one path two port.

I'm trying to find some documentation which is very clear and unambiguous about one path two port, but I haven't succeeded yet.
I don't know enough myself to answer the question about how it works. If I could then I would be off building VNA's for a living :)

But anyway, here is a page from scikit-rf about it:
https://scikit-rf.readthedocs.io/en/latest/examples/metrology/TwoPortOnePath,%20EnhancedResponse,%20and%20FakeFlip.html

The FakeFlip covers the case of a perfectly symmetric component.

I think that page might have been what sowed the seed in my head in the past that this type of cal could correct for all errors. This comment is what I remember:

Quote
Full Correction (TwoPortOnePath)
Neglecting the connector uncertainty, this type of correction is identical to full two-port SOLT calibration.

I'm at work, so I can't spend much time on it.





 

Offline ogden

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A symmetric component is a special case of a two port component. In the case of a perfectly symmetric component and fixture then I agree with you - you don't need to reverse the DUT.
Good. If we talk about reversal, then SOLT-calibration of the *fixture* both ways (on S11+S21 VNA) could possibly increase de-embedding precision (of the fixture). This potentially will increase precision of DUT impedance measurements which as we (at last) agreed, do not need to be reversed.
 

Offline hendorog

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A symmetric component is a special case of a two port component. In the case of a perfectly symmetric component and fixture then I agree with you - you don't need to reverse the DUT.
Good. If we talk about reversal, then SOLT-calibration of the *fixture* both ways (on S11+S21 VNA) could possibly increase de-embedding precision (of the fixture). This potentially will increase precision of DUT impedance measurements which as we (at last) agreed, do not need to be reversed.

Good.

Now that we have got past that.

The issue I have been talking about here is how to correct for the load match error in the nano. And of course how much it matters.
 

Offline ogden

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The issue I have been talking about here is how to correct for the load match error in the nano.
Yes, you are talking about that - I noticed. We can continue. As you already learned, reversal of the DUT won't help in our case of symmetric component impedance measurements. What remains - nothing much actually. Psuedo-Full Correction (FakeFlip) you linked seems like possible solution to improve something here, yet article does not cover details. You are welcome to explain how it works and what could be actual improvements using FakeFlip calibration.

One thing for sure that can be improved - return loss of NanoVNA ports. Currently RL of Port2 is kinda poor (to say it politely): @299MHz it improves from -28dB (48.1+j3.1 Ohm) to -48dB (49.9+j0.4 Ohm) by adding quality 50Ohm 10dB matching pad. Port1 matching can be inferior as well. Disclaimer: I talk about NanoVNA I have which is black *clone* with no shields.
 

Offline hendorog

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The issue I have been talking about here is how to correct for the load match error in the nano.
Yes, you are talking about that - I noticed. We can continue. As you already learned, reversal of the DUT won't help in our case of symmetric component impedance measurements. What remains - nothing much actually. Psuedo-Full Correction (FakeFlip) you linked seems like possible solution to improve something here, yet article does not cover details. You are welcome to explain how it works and what could be actual improvements using FakeFlip calibration.

One thing for sure that can be improved - return loss of NanoVNA ports. Currently RL of Port2 is kinda poor (to say it politely): @299MHz it improves from -28dB (48.1+j3.1 Ohm) to -48dB (49.9+j0.4 Ohm) by adding quality 50Ohm 10dB matching pad. Port1 matching can be inferior as well. Disclaimer: I talk about NanoVNA I have which is black *clone* with no shields.

Excellent, there is no need to proceed any further in that case.
 

Offline ogden

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Excellent, there is no need to proceed any further in that case.
Why don't you explain how FakeFlip works.
 

Offline hendorog

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Excellent, there is no need to proceed any further in that case.
Why don't you explain how FakeFlip works.

I can't help you there.

But I did keep looking for a good doc, and then I found this video which covers it perfectly I think.

 

Offline ogden

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Why don't you explain how FakeFlip works.
I can't help you there.

But I did keep looking for a good doc, and then I found this video which covers it perfectly I think.
Thanx! Apparently we both looked. I found this wiki page which covers your case perfectly I think.

 

Offline virtualparticles

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This is a real can of worms. One-Path, 1-port calibration is also called "Enhanced thru" calibration. The two main contributors to S21 uncertainty are "Transmission Tracking" and "Isolation". The Isolation error, or the leakage from port 1 to port 2 within the VNA is usually below thermal noise in the measurement bandwidth of most VNAs. Unfortunately, the isolation of the Nano is quite awful, so this calibration must be performed. After calibration, the isolation cal should hold for an hour or so. After that one will begin to see the noise creep higher at the high end of the frequency band.

Transmission tracking is approximately equal to the sum of the products of the Raw Port 1 match and the Residual Port 2 match and the Raw Port 2 match and the Residual Port 1 match. To clarify the terms here, Residual means the "apparent" value after mathematical correction has been applied. A One-Path, 2 port VNA does not have a Residual Port 2 match calculation so the Transmission Tracking becomes a function of the sum of the Raw source and load matches alone. This results in ripples in the S21 measurement.

Thanks

BW
 
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