Need help from the old farts! :D How were dense DIP boards routed way back then?

[Benta]

The 68010 had a relocatable IV table.
Being able to rewrite the interrupt vectors on the fly is important for many RTOS.

System design, both hardware and software, is a new frontier for me. Why is it important?

It's partial gobbledygook. No one ever rewrites IVs "on the fly".

What happens is that when the 68k (applies to other architectures as well) comes out of reset, all vectors are stored in ROM (starting at 0x0000...). Otherwise it wouldn't boot.
Normally the vectors will be the lower part of a larger boot ROM containing all the startup code.

Classic 68k systems will then copy the full contents of this ROM to RAM somewhere in the memory map.

The external memory address decoder will have a hardware function to remap the relevant RAM area to 0x0000... and either disable the ROM or remap is as well.

Now all exception vectors and boot code are in RAM, but still at 0x0000...

This allows next step booting of operating system etc. that needs its own exception vectors like interrupts.

[MarkS]

Oooohhh! That makes perfect sense! It may not be necessary in this project, but will be in the next one. Thank you for the explanation!

[Benta]

Exactly.
If you have an embedded 68k system with fixed functionality in ROM and RAM just for data, the memory map modification HW is unnecessary.
But you'll still need HW for AS, LDS, UDS and DTACK.

[MarkS]

Exactly.
If you have an embedded 68k system with fixed functionality in ROM and RAM just for data, the memory map modification HW is unnecessary.
But you'll still need HW for AS, LDS, UDS and DTACK.

My understanding about DTACK is that it was necessary when memory was much slower than today. Supposedly, I can ground it and be fine. I'm not opposed to implementing the circuitry, but I'd like to avoid it if possible.

[srb1954]

Exactly.
If you have an embedded 68k system with fixed functionality in ROM and RAM just for data, the memory map modification HW is unnecessary.
But you'll still need HW for AS, LDS, UDS and DTACK.

My understanding about DTACK is that it was necessary when memory was much slower than today. Supposedly, I can ground it and be fine. I'm not opposed to implementing the circuitry, but I'd like to avoid it if possible.

You will need DTACK if you intend to use any of 68K peripheral chips.

For sufficiently fast memory you can wire DTACK low, or preferably connect it to the memory address decoder so that it only responds in valid areas of the memory map. With this arrangement, and in conjunction with a bus time-out circuit, you can catch runaway programs that access invalid memory areas and re-route the program to a bus error handler routine.

[Benta]

I'm with srb1954 here.
If you're looking to make an absolute minimum 68k SBC, I'd drop all the buffers, they're not really necessary these days. Modern CMOS Flash and SRAM are no big bus loads.

But in my opinion, the following elements are necessary for a well-functioning and robust 68k system:

Clock.
Interrupt encoder (74xx148).
Memory decode (74xx139 or 74xx138).
DTACK generator (74xx30 + 74xx04) and associated bus error timer.
RESET/HALT logic.

All this was in earlier days done with a PAL/GAL, but those are out of fashion.

[David Hess]

Some of the truly densely populated boards of old have chips so close you'd think the pins would short out!

...

How was this done efficiently back in the day?

I know what boards you are talking about.  They used 4 or more layers, and blind vias.

[MarkS]

These seems little point in having a manual HALT switch as currently implemented it is largely useless in controlling a program halt with any precision. However, if you add some additional circuitry you can make into a a single step control which could be quite useful for debugging a errant program or tricky interrupt service routines.

Yes, it is a little odd, I agree. The book I'm using for reference shows a debounced reset circuit and below that, a line labeled "single step" tied to HALT. Not too sure what that meant, I duplicated the reset circuitry. Now that I think about it, that truly is pointless. I'd have to press and hold that button once per 10 MHz clock pulse!

So, what would a single step circuit look like? I can work it out myself, I'm sure, but I don't even know where to begin.

[bson]

In general, ideally you want to place the buffers next to the header, attach the outputs 1:1 to the nearest header pin, then pick buffer input pins for signals as you route.  Unfortunately, KiCad doesn't make this easy as you have to go to the schematic to draw lines, then update the PCB and route them.  Ideally, you'd route buses to buffers on the PCB to then get a rats nest in the schematic, and then add the bus connections there.  Sometimes for some design elements PCB-first is really the best approach...

If acceptable you can also route the signals to buffers and buffers to the header and just let header signals fall where they may.  This would yield the absolutely most compact layout, but at the expense of a bit of bus fragmentation on the header...

[Benta]

Yes, it is a little odd, I agree. The book I'm using for reference shows a debounced reset circuit and below that, a line labeled "single step" tied to HALT. Not too sure what that meant, I duplicated the reset circuitry. Now that I think about it, that truly is pointless. I'd have to press and hold that button once per 10 MHz clock pulse!

So, what would a single step circuit look like? I can work it out myself, I'm sure, but I don't even know where to begin.

You need to remember that the RESET and HALT pins have several functions, and that both signals are bidirectional.
For a HW reset, you need to assert RESET and HALT simultaneously (mandatory).
For resetting external peripherals, RESET is an output after executing the RESET instruction (seldom used).
For the "big red mushroom" emergency stop button, HALT may be used as an input (very seldom used).
For an LED indicating a catastrophic failure (double bus fault), HALT can be used as output (very often used).

Single-stepping will normally be done using interrupts, much cleaner.

[Benta]

PS: I hope you have this already:
https://www.nxp.com/docs/en/reference-manual/MC68000UM.pdf

[MarkS]

PS: I hope you have this already:
https://www.nxp.com/docs/en/reference-manual/MC68000UM.pdf

Oh heck yeah! But it's a dense read.

[Benta]

Oh heck yeah! But it's a dense read.

I know what you mean. Looking at the 68000 is the mid-80s, I gave up on it as well - too complex.
But around 1990, a mentor who understood the Motorola Computer Group's (and the associated Architecture guys) thinking behind the 68K took me under his wings. Bingo!
When you understand the philosophy behind the CPU, everything about it suddenly becomes logical and inevitable somehow. Many idiosynchrasies come from squeezing everything into a 64-pin package.
The fully-fledged 68020 didn't have that problem.

[KubaSO]

Also, when things are twisted, flip the layer. Yep, sometimes that's what it takes to make layout easy. And make sure you can get one trace between each pair of pads. At least one. Two if you make the pads quite narrow and go for thin traces, say 7+7mil trace/space

[KubaSO]

The problem is that KiCAD has very few footprint options. I did reduce it to the footprint with the smallest available pads, but if I wanted the pads smaller, I'd have to make my own footprints and I really don't want to do that. I'm using KiCAD's default track width of 0.25mm, which very easily fits though even the larger footprint's pads.

I don't think I laid out anything in KiCad or Altium or anything else that didn't take some footprint modifications and new schematic symbols. Especially schematic symbols - my pet peeve. I have a seething hatred for the modern "everything is a box with net labels sprinkled around" approach. Yuck.

You'll not want any defaults. Create at least a project-specific footprint library and keep all the tweaked footprints there. Measure actual dimensions of the pins you'll be soldering - whether directly or via milled sockets - and dimension things based on that + some radial clearance between pin and hole. 10mils diametric clearance should be fine if the holes are dimensioned as finished sizes.

Look up the chosen PCB manufacturer service for minimum trace and space. For logic signals you may well use the thinnest to go between pads.

I have several DIP designs that had "routing dots" between the pads. Those dots were tiny non-connected pads that maintained the trace and space as needed, and I could then easily route traces through them. The pads were back-annotated on the last schematic sheet, and weren't a big deal once I had the process worked out. Yes, in KiCad.

PCB layout is an art. You won't do much good without some work to figure out a good process that gets good results. About the only footprints I haven't had to touch were SMD ones that have IPC-derived sizing and the reflow and hand-soldered variants are spot-on. For through hole stuff? Even the same axial part may need a couple different pad/hole size options, so yeah, you'll be having that footprint editor open and busy. It's part of the job.

[MarkS]

I have several DIP designs that had "routing dots" between the pads. Those dots were tiny non-connected pads that maintained the trace and space as needed, and I could then easily route traces through them. The pads were back-annotated on the last schematic sheet, and weren't a big deal once I had the process worked out. Yes, in KiCad.

This is an absolutely brilliant idea! You've sold me! I don't WANT to make my own footprints, but that is a great reason to do so! Thank you very much for the idea!

[KubaSO]

Here's a 6.15x6.5 4-layer board I did a while ago for a discrete Z80-reimplementation. This is a 4-bit bit slice of the register file. Every DIP in the picture is for a CD4000-family chip Also, every single pin on the card connector is used up, with just the minimal number of GND and VCC repeats needed for signal integrity. The capacitors are surface-mount 1206 on the bottom side. Through-hole capacitors waste a lot of real estate on such tight boards. Top layer mostly has vertical traces, bottom layer mostly horizontal traces. The internal planes are GND and VCC.

Since this was a single-cycle-per-instruction Harvard implementation, with no pipeline, the register file had to have multiple read and write ports according to what the instruction set needed. This thing can run at about 4MHz from 12.5V supply. 4MIPS. 18 registers in total, with alternate register file included. The register file is 4-slices wide, so the data paths are all 16-bits. That was the only way to do 4MIPS with 70s discrete CMOS logic. Data and program memories also had multiple ports... I'm glad this is over, I got in way deeper than I thought it'd take.

To get the ALU fast enough, only two bits fit on a card of the same size. All of it was implemented using 4066 muxes for logic and some 4051s as complementary output buffers to keep the muxes fed with strong inputs

4 slice cards for registers, 8 slices for ALU, 8 slices for code memory and instruction decoder, another 4 slices for data memory, 6 unique cards for the controller, external bus interface, etc. No time to publish the whole thing yet...

[floobydust]

Where are the capacitors 

Oh and not sure if it's been mentioned but one layer is X direction only and other layer is Y direction only for traces, was a common method for routing, back in the day.

[Agent24]

The problem is that KiCAD has very few footprint options. I did reduce it to the footprint with the smallest available pads, but if I wanted the pads smaller, I'd have to make my own footprints and I really don't want to do that.

You don't need to, you can just edit the pad sizes on the component you need to change. Then you can update all pads on the IC or just change only the ones that need changing.

Assuming you're using v6 or such, make sure the footprint is not selected, then right-click the pad and choose "properties" and edit the pad size etc. Once done, right click the pad again, choose "Push pad properties to other pads" and use the options there as appropriate.

[jonpaul]

Rebonjour,
 In 1970s..1990s,with double sided boards it  was Common to use jumpers, route  2..3 traces between adjacent DIP pads, with special narrow elongated pads.

Jon

PS:  post title is insulting. Kindly edit out "Old farts"

I suggest it is rude.

 

[Nusa]

Well, all of us who predate the internet are reasonably considered "old" now. And everyone farts. It's no worse than greybeard. Which is also true, although not that different from the blonde beard I used to have.