Need help from the old farts! :D How were dense DIP boards routed way back then?

[MarkS]

I'm working on several projects based on the MC68000. To make my life easier (HA!) I am separating everything into multiple development boards. To keep with the retro look and feel, I'm using as close to 100% DIP packages as possible.


Right now I'm working on the processor board. I have all of the buses broken out to female headers via 74LVC245's. No matter how I orient the processor or transceivers, the ratsnest is just a total twisted mess. And I'm giving quite a bit of space between components! Some of the truly densely populated boards of old have chips so close you'd think the pins would short out! I've tried rotating and moving the transceivers and CPU, but all that does is move the twisted mess.


How do I tackle this? I'm going 4 layers, just because of this issue, but in reality, 2 layers should suffice. I can reorder the nets so that they line up better with the transceivers coming from the CPU, only that twists them between the transceivers and headers. I could make the bus out of order at the headers, but that complicates development and ensures nasty errors when wiring between development boards.


How was this done efficiently back in the day?

[mariush]

Seems simple to me : U5 to U11 have to be rotated 90 degrees.   Align them as close as possible to the top headers so you more or less have traces go directly from DIP chips to the headers.

You can route some traces UNDER (inside the footprint of ) the microprocessor and some traces can go on the bottom layer of the pcb.  Especially where a bunch of traces have to be flipped/reversed ... use vias to route them to other layer and then you no longer have to reverse them.

If you're reluctant to use VIAs you can use 0 ohm resistors / jumper links to jump over traces where needed.

If the order of the headers is not critical, maybe they can be rearranged to work better, for example CONTROL BUS and the one to the left and U5 and U8 may be better all the way to the right.

[jonpaul]

narrow down your pads, route traces in between two pads

j

[MarkS]

Thank you! That got me in the right direction!

[Terry Bites]

Manual routing is efficent if you have the skills!
Mariush is right.
Placement is everything. Rotate the 245s
Make the pads 64 thou or less. You'll get a 16 thou track through the pin spacing with ease.
Mil to you.
68000 thats old fart territory alright!

[MarkS]

Manual routing is efficent if you have the skills!
Mariush is right.
Placement is everything. Rotate the 245s
Make the pads 64 thou or less. You'll get a 16 thou track through the pin spacing with ease.
Mil to you.
68000 thats old fart territory alright!

The problem is that KiCAD has very few footprint options. I did reduce it to the footprint with the smallest available pads, but if I wanted the pads smaller, I'd have to make my own footprints and I really don't want to do that. I'm using KiCAD's default track width of 0.25mm, which very easily fits though even the larger footprint's pads.

68000 is old fart territory, but I'm 46, so I'm not too far off and my first computer was a Mac 512KE. I learned to program on the 680xx line of processors, including 68K assembly. It holds a special place in my heart.

[MarkS]

Wait a minute!   I meant to rotate the chips.  Back to the drawing board... Fortunately I didn't get far.

[m k]

Back in the day simple cost reduced two layer MCU modules were already fine line, two tracks between pads.
There pads are quite small, maybe a chat with the maker is required.
Obviously width is more critical with semi unknown outside connections.

[MarkS]

MUCH better!

[pcprogrammer]

With a bit of practice you can reroute and get rid of the five vias near pin 1 of the cpu. And like m k wrote it is possible to route two tracks between the pads when you make the track width and the pads smaller.

Since you are doing 4 layer you can forget about the power and ground which makes things much easier.

I did this kind of stuff 30 years ago with PLCC84 and DIP sockets (SAB80537 MCU and XC3042 FPGA) with Protel PCB. Would think that it should be easy to do now with current production processes.

Edit: Added some pictures as proof 

[james_s]

It was all done manually back in the day, drafted by hand without any CAD tools. I don't recall seeing many 4 layer boards back in the DIP era, just PC motherboards starting around the early 80s. Stuff like arcade games were all just double sided boards and errors corrected by bodge wires were common. I have one board where it's obvious a small trace was meant to go on the other side because it crosses over another trace and they had to cut it and replace it with a wire.

[mikeselectricstuff]

General rule for DIP boards - have all chips facing the same way, and use one layer for horizontal routing, and another for vertical. Don't worry about how many vias this takes. Only break the horizontal/vertical rule at the edges where there is no chance of blocking. 
That way you have multiple options for any route, based on minimising congestion.
If things get tight, you can reduce the pad size on the top layer without affecting solderability, so having the top layer be routed perpendicular to the IC orientation is probably best for density - you may be able to do 2 traces between each pad. 

4-layer makes this a lot easier as all your power/grounds disappear from the picture.

[mikeselectricstuff]

Where you have things like buffers, remember all gates are equivalent, so you may be able to seriously simplfy by juggling these around - nailing down the gates used at the schematic stage can constrain you too much. Ditto SRAMs, where any address or data line can be swapped with another.
 

[mariush]

MUCH better!

Unless you have to squeeze them so much vertically, I think you could do better by having U7 and U12 shifted to the left, so that U7's first two pins would be inline with U8.
Something like this (excuse the paint skills):

edit : unless you make it 4 layers, also be careful to leave some spacing to route power to the chips. I'm thinking you'll probably want to have the bottom as much ground fill as possible and break that fill just to have small breaks for traces that have to jump over traces, or traces that have to go short lengths. \
Another practice in the old days was for one layer to have traces routed mostly vertically, and the other layer to have traces mostly horizontal. Dave can probably explain well why this was done.

[tooki]

The problem is that KiCAD has very few footprint options. I did reduce it to the footprint with the smallest available pads, but if I wanted the pads smaller, I'd have to make my own footprints and I really don't want to do that.

I strongly suggest embracing DIY footprint (and schematic symbol) design as early as possible, because the moment where you need some footprint that isn’t available WILL come sooner than you think! But it also gives you the flexibility to do what you need, like using oval pads for DIPs instead of the abominably difficult-to-hand-solder-nicely circular pads with nearly no pad surface.

[jonpaul]

We used Bishop red/blue tapes on mylar size b,c or d with registration pins.

On a 2x or 4x scale, one or even two traces could pass between adjacent DIP 0.100" pins.

My last PCD CAD was OrCad and Altium.

Bon Chance

Jon ( NOT AN OLD FART)

[MarkS]

The problem is that KiCAD has very few footprint options. I did reduce it to the footprint with the smallest available pads, but if I wanted the pads smaller, I'd have to make my own footprints and I really don't want to do that.

I strongly suggest embracing DIY footprint (and schematic symbol) design as early as possible, because the moment where you need some footprint that isn’t available WILL come sooner than you think! But it also gives you the flexibility to do what you need, like using oval pads for DIPs instead of the abominably difficult-to-hand-solder-nicely circular pads with nearly no pad surface.

I do my own quite frequently. I just don't like doing it if it can be avoided.

[MarkS]

Jon ( NOT AN OLD FART)

It's OK to admit it!

[Benta]

Old Fart reporting for service!!

Frankly, we started with paper and pencil, sketching possible placement for best layout.
You don't seem to appreciate the fantastic leap forward the "rat's nest" functionality in CAD was!
Rotating and dragging parts until the chaos begins to straighten itself out is a blessing. See that you use it properly! (which your original post did NOT show).
Be glad to have it, we didn't.

[MarkS]

Thanks for all the help! It's coming together!

See that you use it properly! (which your original post did NOT show).

I agree! That's why I was stumped and why I asked. I knew I was doing something wrong and that it couldn't possibly be that hard, and I was and it wasn't.

Be glad to have it, we didn't.

Oh, I am! I cannot even imagine what you guys went through!

[DrGeoff]

I did many 68K boards back in the 1980's. All on 2-layer hand routed (some with red/blue tape) boards.
First thing to do is to orient your chips on a grid and located correctly to make routing easier.
Second thing to do is route the power grid. Two traces down the middle of each chip row with crosses at each end and, if a long board, in the middle too.
Add a decoupling cap to each chip across these power rails.
Now start routing the signals. 10 thou track and spacing was usually used for most signals on digital boards.

[profdc9]

I have a Z80 single board computer with many 40 pin DIP ICs on it close together.

You can see how I routed things.

http://www.github.com/profdc9/Z80SBC

Basically, use 0.35 mm wide traces or less, place chips so that particular bus lines are near the same bus lines of other chips, cluster traces so that you can jump them with vias over other traces more easily.

[shakalnokturn]

On densely populated power-hungry fast TTL boards you'd sometimes find vertically mounted power strips running in-between rows of IC's (can't remember the exact name nor find an example online).

They had the advantage of taking some of the heavier tracks off the board to free space for the logic routing, I'm not certain but seem to remember some dual power rails doubled-up as decoupling capacitors.

[MarkS]

I have a Z80 single board computer with many 40 pin DIP ICs on it close together.


You can see how I routed things.


...snip...


Basically, use 0.35 mm wide traces or less, place chips so that particular bus lines are near the same bus lines of other chips, cluster traces so that you can jump them with vias over other traces more easily.

That's how I plan on routing the board once I'm done with prototyping. The board I'm designing here is just the processor so that I can connect it to memory and IO boards and breadboards for prototyping. It will be much easier when I am not routing to transceivers and headers.


Anyway, I am about 90% done! Thanks for all the help!

[MarkS]

On densely populated power-hungry fast TTL boards you'd sometimes find vertically mounted power strips running in-between rows of IC's (can't remember the exact name nor find an example online).

They had the advantage of taking some of the heavier tracks off the board to free space for the logic routing, I'm not certain but seem to remember some dual power rails doubled-up as decoupling capacitors.

So, basically heavy gauge bare copper wire? Hmm.... Not a bad idea.