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Need PCB placement EMC advice for analog/digital 4 layer board
Axk:
I'm doing an e-bike power meter as a hobby project.
The design might be a bit of an overkill for what I'm doing, but this is a hobby project and I need to learn something so it wouldn't be fun to do the simplest and most practical thing. Max current - 20A, ADC - 12bits (1LSB - 5mA), (over)sampling rate - 1.5Msps, bandwidth - 100KHz, digital clock - 50MHz.
I would like to get as good resolution as possible, down to the limits of the ADC if possible.
I'm planning to use a 4 layer board, 2 signal layers (preferably all signals on the top) and 2 power planes.
The design contains a 5 mOhm shunt resistor and a current sense amp with a unity gain buffer between the output of the current sense amp and an ADC.
A voltage divider to measure the voltage (54.6V max) with a unity gain buffer (a double op-amp shared with the current sensing) and the same (dual channel simultaneously sampling) ADC (1.5Msps, 12 bits). The opamp's negative rail is powered from a negative charge pump to get a true zero output.
The current sense amp is powered directly from the 50V supply while everything else from a 3.3V regulator (with a discreet heat-sinked TO-220 NPN, the whole board will be attached to a 3mm aluminum plate with the TO-220 bolted to the plate directly off-board).
From the ADC it goes to an FPGA (Lattice Mach XO2) and then a Bluetooth module to send the info to a phone.
I've done a project with an FPGA so I should be able to pull the FPGA part off.
My main concern is analog signals and EMI between the digital and analog sections of the board.
I've done some reading on EMC, low frequency vs high frequency ground plane signal return paths, ground loops, bypassing and so on on learnemc.com/tutorials but I'm a bit overwhelmed as to what is more or less important in my particular case.
Besides digital/analog signal return paths crossing on the ground plane I'm also concerned about analog and digital circuitry sharing the same voltage regulator (50V -> 3.3V) and CMOS transistor switch (1 Ohm). The digital FPGA and Bluetooth module sharing the regulator with the Buffer amp and the ADC, the current sense amp is powered directly from the 50V supply but is still sharing the switch with everything else.
I'm attaching the screenshots of the schematics and my first placement attempt.
The board in 10cm long, the smallest passives are 0603s.
The current is going from the bottom connector to the top on the left of the board.
POWSW - power switch, supplies everything else with 50V (the connector in this section if for external switching);
CS - current sense amp;
R6/R7 - the voltage sensing divider;
VREG - 50V-3.3V regulator (with holes for wires to go on the bottom to an externally mounted TO-220 just off the left edge of the board)
BUF - the unity gain buffer dual op-amp;
NEGV - the negative charge pump for the op-amp's negative rail;
In my understanding the most EMI sensitive connections would be from the shunt to the current sense amp (0.02 mV/LSB) and from the current sense amp (the voltage across R10, 1mA full scale) to the buffer (0.6mV/LSB) so these should be as short traces as possible and away from digital currents.
Thus I'm placing the current sense amp right next to the shunt and the buffer right next to the current sense amp.
I'm placing the digital portion's connections at the top so that the digital high frequency currents flow from right to left across the top of the board to the regulator on the top left not interfering with the currents between the regulator and ADC/buffer.
I would put a slot in the ground/power planes horizontally on top of ADC/buffer to further separate them from the digital currents but this then creates a loop for the return signal currents going between the FPGA and ADC so the digital currents will go near the analog sections currents anyway.
Any advice is appreciated if my placement is any good.
DannyTheGhost:
I think you are too concentrated on EMC problem that you don't see more important details to your project.
First of all, you don't have that much components and almost no high-speed signal lines to go for 4-layer board
Secondly, if I were you, I would worry for PCB traces handling 20A of current more that EMC
In your case I'd rather go for star-ground configuration (digital and analog power planes and traces are connected only near power supply) which will deal with all noise almost perfectly
Also, no need for components to be so far from each other
Axk:
@DannyTheGhost, I think a short 1 cm wide (3cm long) trace should handle the current.
I'm going to have a 50MHz digital clock for the ADC, I thought it qualified as high speed.
Axk:
One thing I've just noticed is the current sense amp is between the regulator and the switch so all the current from the switch to the regulator and back will go under the most sensitive current sensing amp area...
Need to move the switch to the top somehow so that it's next to the regulator I suppose...
DannyTheGhost:
Ground plane right under 'high-speed' digital lines should be enough for your application.
By the way, are you really sure that you need that kind of bandwidth for current sensing? You won't see much more with this bandwidth except additional noise
Edit: if you reconsider your bandwidth requirements you could also lower your clock speed
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