| Electronics > Projects, Designs, and Technical Stuff |
| Need to build On-screen display for VGA |
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| GeorgeOfTheJungle:
To make an OSD he's going to need a µC anyway. |
| Yansi:
I do not think that making an OSD is a requirement for uC ;) Text and graphics rendering can pretty sure be done even in the FPGA. Depends on the application of course. Just wanted to make a point, that a a $5 FPGA would make for a pretty OSD overlay generator. $5 MCU would be likely struggling to do the job properly, with you losing precious time on creating hacks over hacks to make that work. |
| Scrts:
--- Quote from: GeorgeOfTheJungle on February 06, 2019, 04:23:46 pm ---1080p @60Hz HSYNC frequency is ~ 1080*60= 65 kHz, pixel clock ~ 1080*60*1920= 125 MHz, 1080p @30Hz half that: 32.5 kHz and 62.5 MHz. All you need is one parallel in serial out shift register than can run at those pixel clock frequencies. Or two... Any µC can count HSYNCs @ 65 kHz, and load the shift register(s) between lines. --- End quote --- 1080p pixel clock is 148.5MHz usually. I haven't seen a microcontroller that can handle such resolutions. Not even Spansion Traveo series. |
| Yansi:
--- Quote from: Scrts on February 06, 2019, 09:20:46 pm --- --- Quote from: GeorgeOfTheJungle on February 06, 2019, 04:23:46 pm ---1080p @60Hz HSYNC frequency is ~ 1080*60= 65 kHz, pixel clock ~ 1080*60*1920= 125 MHz, 1080p @30Hz half that: 32.5 kHz and 62.5 MHz. All you need is one parallel in serial out shift register than can run at those pixel clock frequencies. Or two... Any µC can count HSYNCs @ 65 kHz, and load the shift register(s) between lines. --- End quote --- 1080p pixel clock is 148.5MHz usually. I haven't seen a microcontroller that can handle such resolutions. Not even Spansion Traveo series. --- End quote --- That is for a rather unusual 85Hz refresh rate. But anyway, the pixelclock is above 100MHz for sure, in any Full HD mode. You will get in trouble trying to hack any MCU for making OSD, at such frequencies. Even the quite high performance MCUs (400MHz Cortex M7, with dedicated video hardware) are way slow for any image processing at such resolutions and pixel clock speeds. You could barely find a peripheral, that could be hacked to accept a 100MHz+ external clocking. Slapping together tons of glue logic (74 series and such) around the MCU will become a major pain at 100+ MHz anyway. Not to begin with the fact that you would need a device to do the TMDS data deserialization and serialization. There aren't many devices on the market to do this. Many of them also closed under NDA. The FPGA is the obvious solution here. Comparatively even cheap and quite simple to use. |
| GeorgeOfTheJungle:
The shift register is the only thing that runs at the pixel clock frequency. And you can choose the pixel clock frequency, it doesn't have to be the same as that of the underlying image, can be whatever you want, a lower or higher pixel rate. The µC's job is to load the pixels into the shift register before the scan line begins, at HSYNC frequencies, it's easy-peasy: no assembly hacks needed whatsoever. By the way, the OP wants RGB VGA, no LVDS, no TMDS, no things of that kind. |
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