Current sense shenanigans with open collector bus level translation

[Nominal Animal]

All I2C/SMBus level translators I know of are limited by how close to ground they can pull the signal level to, because they use voltage level sensing to determine if any other transistors on the same signal line is pulling the signal to ground or not.

I had this wonky idea for open collector bus translation, and would like to know if you've seen this used, know of any references to this technique, or know that this does not work in practice for some reason or another.  I haven't tried it, as it is only an idea at this point:
The high-to-low transition is detected based on the signal voltage level dropping below some specific limit, but the low-to-high transition based on the current over the pull-down current sense resistor.

Basically, the level translator requires resistor ratios R2/R1 and R4/R3 to be known.  R1 and R3 are on the order of 1kΩ to 10kΩ, and R2 and R4 are less than 1Ω.  Analog inputs AIN1 and AIN3 are used to measure both the signal voltage, and the current over R1 and R3.  OUT1 and OUT2 are outputs, and always have the same state (so technically they are a single output).  When high, the MOSFETs Q1 and Q2 conduct, pulling the signal lines down, through current sense resistors R2 and R4.  The current over these resistors is measured using analog inputs AIN2 and AIN4.

In practice, the actual currents are not needed; we only need to know if the signal exceeds some preset threshold voltage, whether the current over R2 exceeds some preset fraction of the current over R1, and whether the current over R4 exceeds some preset fraction of the current over R3.  We really only need to know whether each the four voltage ratios – AIN1/VIN1, AIN3/VIN2, AIN2/(VIN1-AIN1), AIN4/(VIN2-AIN3) – exceed a preset limit or not.



Initially, both signal lines idle high, with OUT1 and OUT2 low (Q1 and Q2 not conducting).  When either (AIN1/VIN1) or (AIN3/VIN2) ratio drops under a preset limit, someone else on the bus is pulling the signal line down, therefore OUT1 and OUT2 are set high so that Q1 and Q2 start conducting and pulling both signal lines close to ground.

When OUT1 and OUT2 are high and Q1 and Q2 are conducting, and (AIN2/(VIN1-AIN1)) (analogous to the ratio of the currents over R2 and R1) or (AIN4/(VIN2-AIN3)) (analogous to the ratio of the currents over R4 and R3) increases above a preset limit, we know Q1 and Q2 are the only ones pulling the signal lines down, and therefore OUT1 and OUT2 must go low to stop Q1 and Q2 conducting.

(This is because when Q1 or Q2 is conducting when there is some other transistor pulling the same signal towards ground, at least some of the current must go via that other transistor thus decreasing the current over the translator pull-down current sense resistor –– assuming R1 and R3 are the only pull-up resistors on their respective signal lines.)

Now, as far as I understand, even this method cannot get much closer to ground than the typical half a volt or so (because the low level the MOSFETs pull the signal down to, must be high enough for at least some of the current to flow through other transistors on the same signal pulling it low, for the translators to detect it), but it will pull both sides of the bus to similar low levels consistently, is fully symmetric, and does not require VIN1>VIN2 or VIN1<VIN2.  It only requires that R1 and R3 be the only pull-up resistors on the bus.