Nfet vs Pfet for external device switching

[3dgeo]

Hi,

I'm designing little CO2 laser control board (24V input) and want to implement 2 PWM power outputs for LED strip (up to 1.5A) and for a pump (up to 1,5A).
Low side switching for external devices "doesn't seems right" at best, so my original intention was to use PNP fets. But gate voltage of those fets is +-25V (absolute maximum) – way too close to supply voltage.
What would be recommended path – try to limit maximum gate voltage via drop out diode (D65) and zener diode (D66) or something similar or just go with NPN?

U4 – Fet driver

P.S. I'm not expert in power stuff.

[dobsonr741]

What are the reservations about the low side driver?

In any case, there are much better MOSFET drivers than the transistor pair - for example: https://ww1.microchip.com/downloads/en/DeviceDoc/mic5011.pdf

It has a charge pump needed for high side and the zener.

The divers can do even more when diving a half bridge, giving a bunch of protections.

[ajb]

There’s really nothing wrong with low side switching of basic loads. If it were something with other connections where that would be a problem, sure, but an led strip or a motor are just fine. You still want high side wiring protection if you’re running those wires through grounded equipment, but that can be the overload protection built in to the power supply in many cases.

That said, you can use N- or P-channel FETs in high-side switching. N-channel typically have lower on resistance and so make more efficient switches, but have the downside of needing a charge pump or similar to provide a gate voltage that’s positive wrt the supply voltage. Fortunately there are ready-made solutions like the one that dobson741 linked.

But it’s worth considering if you really want a FET driver like that. Mostly FET drivers are used to achieve faster switching, which is more efficient, but also more prone to emitting EMI, especially when driving offboard loads with long(ish) wires. You can add filters and other mitigation methods, but simply not switching so fast in the first place can address the problem at the source ( ). It’s a bit less efficient, but that can be mitigated by lower PWM frequencies, and isn’t important for an on/off load, as long as you stay within the SOA of the FET.

When using a P-channel FET on the high side, as you’ve noticed, you can’t just pull the gate to ground from 24V. D65 does kinda help that, but going from 24V to 23.3V when abs max is 25V still leaves you way too tight on margin. Remember that absolute maximum ratings are the line beyond which the datasheet and all guarantees about proper function—let alone performance—go out the window. Your design margin needs to be sufficient to absorb supply voltage tolerance/load regulation and any overshoot caused by load path inductance without getting into that territory. Furthermore, to whatever extent that diode helps you limit the max gate voltage, it reduces your ability to turn the gate off, because it limits the ability of the gate driver to pull the gate to the supply voltage to get Vgs to zero. How much of a problem that is depends on the Vgs(th) of the FET and your switching requirements.

A zener on the gate is better, but should be between the gate and source, because the thing you’re trying to limit is the gate-source voltage. Low speed switching can be as simple as a small low-side transistor that pulls the gate/zener cathode towards ground by a suitable resistor.

Simplest solution is still a low-side N-channel FET, though.

[3dgeo]

There’s really nothing wrong with low side switching of basic loads. If it were something with other connections where that would be a problem, sure, but an led strip or a motor are just fine. You still want high side wiring protection if you’re running those wires through grounded equipment, but that can be the overload protection built in to the power supply in many cases.
 

– this is my main concern, everything will be grounded to reduce 20 KV laser EMI. But it seems there is no other way as bootstrapping will not do as pump has its own electronics and PWM will probably mess with its brains.

When using a P-channel FET on the high side, as you’ve noticed, you can’t just pull the gate to ground from 24V. D65 does kinda help that, but going from 24V to 23.3V when abs max is 25V still leaves you way too tight on margin. Remember that absolute maximum ratings are the line beyond which the datasheet and all guarantees about proper function—let alone performance—go out the window. Your design margin needs to be sufficient to absorb supply voltage tolerance/load regulation and any overshoot caused by load path inductance without getting into that territory. Furthermore, to whatever extent that diode helps you limit the max gate voltage, it reduces your ability to turn the gate off, because it limits the ability of the gate driver to pull the gate to the supply voltage to get Vgs to zero. How much of a problem that is depends on the Vgs(th) of the FET and your switching requirements.

Yeah, I knew when I was adding them that those two diodes is like pissing on raging fire...
I really don't need PWM on those outputs, just thought would be nice feature, slow switchin is fine so a small relays would also do?

[ajb]

There’s really nothing wrong with low side switching of basic loads. If it were something with other connections where that would be a problem, sure, but an led strip or a motor are just fine. You still want high side wiring protection if you’re running those wires through grounded equipment, but that can be the overload protection built in to the power supply in many cases.
 

– this is my main concern, everything will be grounded to reduce 20 KV laser EMI. But it seems there is no other way as bootstrapping will not do as pump has its own electronics and PWM will probably mess with its brains.

Well if you can't PWM the pump, then you can't PWM the pump, but none of that means you can't/shouldn't just use low-side switching to turn it off and on. 

I really don't need PWM on those outputs, just thought would be nice feature, slow switchin is fine so a small relays would also do?

Sure, you could use relays if you want.  But a transistor would be perfectly fine too.

[3dgeo]

Do I understand this correctly – the problem in my original picture can be fixed by connecting U4 (gate driver) C2 pins not to GND but to higher voltage, lets say 5V or 12V (same reference)?

I have buck converter on the board that at the moment created 12V, is it OK to connect like in the picture? Will there be any negative effect on 12V line by doing this?
If circuit below is valid I would like to reduce 12V rail to 5V ( I assume reducing it to 3.3V is a bit too low for this purpose?).

[Zero999]

That gate driver IC is just a pair of emitter followers. It lacks the necessary level shifting to control a P-channel MOSFET on 24V, using a lower voltage control signal.

What logic level is the PWM signal? Another transistor and a couple of resistors are required to shift the signal to your driver IC.

Here's an example. In your case, Q2 and Q3 can be replaced by your MOSFET driver IC. The voltage into the MOSFET is R2*(V2-0.7)/R1, about 6.5V when V2 is 5V, in this case. Alter the ratio of R1 and R2 for a different gate driver voltage.

[ajb]

Aside from the lack of level shifting, what you have sketched out would probably work, but there are a couple of things to think about:

- If you were to try to turn the transistor on while the 12V supply was off, you would still end up violating Vgs(max).  So ideally you'd want to provide some sort of lockout, which could be done in software, or by powering whatever is providing the PWM/control signal from that 12V supply. 

- Probably not an issue for your specific application but: Most voltage regulators can only source current, meaning they can only raise their output voltage against some sort of load that is connected to a lower voltage (usually ground).  What they can't do is sink current from a load connected to a higher voltage.  By placing your gate drive circuit between the +12V and +24V rail that's exactly what you've created.  You could think of the buck converter and the gate drive circuit as being in parallel between +24V and +12V, which means they're in series with the load between +12V and ground.  That means that the current through the 12V load is the sum of the current through the gate driver subcircuit and the current provided by the buck converter: I_load = I_gd+I_buck.  Or rearranging, I_buck = I_load-I_gd, which shows that the buck converter supplies the difference between the 12V load and the gate driver current.  As long as I_load>=I_gd, then everything's fine, but if the gate driver current ever exceeds the load current, then the voltage on the 12V rail is going to start increasing due to the excess current. 

Zero999's circuit would certainly be a simpler way to go, though, since it sidesteps both of those issues entirely.

[3dgeo]

12V rail was for Nfet gates, with Pfets that rail will be 5V, not 12V. 5V further will be step down by linear regulator to 3.3V for MCU.

What logic level is the PWM signal? Another transistor and a couple of resistors are required to shift the signal to your driver IC.

Oh, I need a gate driver for my gate driver... 
Logic level can be 5V (open drain) or 3.3V (push pull).

- If you were to try to turn the transistor on while the 12V supply was off, you would still end up violating Vgs(max).  So ideally you'd want to provide some sort of lockout, which could be done in software, or by powering whatever is providing the PWM/control signal from that 12V supply. 

MCU will be powered from that lower rail.

- Probably not an issue for your specific application but: Most voltage regulators can only source current, meaning they can only raise their output voltage against some sort of load that is connected to a lower voltage (usually ground).  What they can't do is sink current from a load connected to a higher voltage.  By placing your gate drive circuit between the +12V and +24V rail that's exactly what you've created.  You could think of the buck converter and the gate drive circuit as being in parallel between +24V and +12V, which means they're in series with the load between +12V and ground.  That means that the current through the 12V load is the sum of the current through the gate driver subcircuit and the current provided by the buck converter: I_load = I_gd+I_buck.  Or rearranging, I_buck = I_load-I_gd, which shows that the buck converter supplies the difference between the 12V load and the gate driver current.  As long as I_load>=I_gd, then everything's fine, but if the gate driver current ever exceeds the load current, then the voltage on the 12V rail is going to start increasing due to the excess current. 

– this is exactly what I had in mind when asking if there will be any negative effects.
I assume there will be high current spikes on gate charge/discharge, but average current shouldn't be a problem with enough filtering even with only linear regulator (should "eat" voltage spikes too?) and MCU being "down the line"? I mean if, as you've written, I_load>=I_gd. MCU should draw at least 50mA, status LED will add few mA.

Working with Pfets is pain...

[ajb]

- Probably not an issue for your specific application but: Most voltage regulators can only source current, meaning they can only raise their output voltage against some sort of load that is connected to a lower voltage (usually ground).  What they can't do is sink current from a load connected to a higher voltage.  By placing your gate drive circuit between the +12V and +24V rail that's exactly what you've created.  You could think of the buck converter and the gate drive circuit as being in parallel between +24V and +12V, which means they're in series with the load between +12V and ground.  That means that the current through the 12V load is the sum of the current through the gate driver subcircuit and the current provided by the buck converter: I_load = I_gd+I_buck.  Or rearranging, I_buck = I_load-I_gd, which shows that the buck converter supplies the difference between the 12V load and the gate driver current.  As long as I_load>=I_gd, then everything's fine, but if the gate driver current ever exceeds the load current, then the voltage on the 12V rail is going to start increasing due to the excess current. 

– this is exactly what I had in mind when asking if there will be any negative effects.
I assume there will be high current spikes on gate charge/discharge, but average current shouldn't be a problem with enough filtering even with only linear regulator (should "eat" voltage spikes too?) and MCU being "down the line"? I mean if, as you've written, I_load>=I_gd. MCU should draw at least 50mA, status LED will add few mA.

Yep, the gate driver should only consume an appreciable amount of current during the brief period of time when the PFET is transitioning between off and on state.  That pulse of current is unlikely to make a significant dent in the output caps on the buck regulator, and likely averages out to a pretty low level over time.  Hence unlikely to be a problem for you in this case, but in other cases, or if you ended up with a gate driver that had some particularly high quiescent current and a 12V load that has a particularly low quiescent current, it could be an issue.  Sounds like you're good there 

[3dgeo]

Here's an example. In your case, Q2 and Q3 can be replaced by your MOSFET driver IC. The voltage into the MOSFET is R2*(V2-0.7)/R1, about 6.5V when V2 is 5V, in this case. Alter the ratio of R1 and R2 for a different gate driver voltage.

What do you mean by "The voltage into the MOSFET...", perhaps you meant "MOSFET driver" not "MOSFET"? Driver is fine with voltages up to 40V so why 2 resistors (R1,R2) are needed? Why only R2 (perhaps at a higher value) and a Q1 would not do?

P.S. shouldn't be Q3 Q2 swapped?

[Zero999]

Here's an example. In your case, Q2 and Q3 can be replaced by your MOSFET driver IC. The voltage into the MOSFET is R2*(V2-0.7)/R1, about 6.5V when V2 is 5V, in this case. Alter the ratio of R1 and R2 for a different gate driver voltage.

What do you mean by "The voltage into the MOSFET...", perhaps you meant "MOSFET driver" not "MOSFET"? Driver is fine with voltages up to 40V so why 2 resistors (R1,R2) are needed? Why only R2 (perhaps at a higher value) and a Q1 would not do?

Your driver is just two emitter followers, like Q2 and Q3 in my circuit. The problem is not the driver, but the MOSFET gate voltage rating.

P.S. shouldn't be Q3 Q2 swapped?

No, they would blow up. Again Q2 and Q3 represent the transistors in your driver. Refer to the data sheet.

[dobsonr741]

The best “Everything You Always Wanted to Know About MOSFET driving (But Were Afraid to Ask) guide: https://reipooom.files.wordpress.com/2011/08/mosfet-must-read-2-slup169.pdf

The applicable simplest solution is fig. 19 for 3dgeo’s case, given the seldom on/off no PWM scenario.

[3dgeo]

I clearly know way too little about transistors...

I've implemented it in my schematics, can I use DTC123JE as a Q1 (Q4 in my picture) as I already have it in BOM?
Will FET fall/rise time suffer from this driving circuit? What would be recommended value for "R?" gate resistor?

The best “Everything You Always Wanted to Know About MOSFET driving (But Were Afraid to Ask) guide: https://reipooom.files.wordpress.com/2011/08/mosfet-must-read-2-slup169.pdf

The applicable simplest solution is fig. 19 for 3dgeo’s case, given the seldom on/off no PWM scenario.

You mean something like this (R1=R2=5K)?

[dobsonr741]

If your PWM is not a high frequency, let's say less than few KHz, the dissipation caused by the not-so-fast gate driver is acceptable. What's the MOSFET - did you choose one already?

You mentioned driving a pump - is it an inductive load? If so, I recommend more precautions on the output to suppress transients/peaks.

[3dgeo]

If your PWM is not a high frequency, let's say less than few KHz, the dissipation caused by the not-so-fast gate driver is acceptable. What's the MOSFET - did you choose one already?

You mentioned driving a pump - is it an inductive load? If so, I recommend more precautions on the output to suppress transients/peaks.

PWM is not required, it would be nice feature and I'll probably implement Zero999 circuit just to see and test how it works.

Pump is not intended to be PWMed, but I've added flyback diodes on LED and Pump screw terminals just in case.

[Zero999]

I clearly know way too little about transistors...

I've implemented it in my schematics, can I use DTC123JE as a Q1 (Q4 in my picture) as I already have it in BOM?
Will FET fall/rise time suffer from this driving circuit? What would be recommended value for "R?" gate resistor?

That transistor is unsuitable because it has built-in bias resistors. You need just a plain transistor, without any built-in resistors, such as the BC847. Also stick to standard resistor values for R1 and R2: 1k and 4k3 or 4k7 will be fine.

The gate resistor should be something like 10R to 47R. It's just there to damp any resonance.

The best “Everything You Always Wanted to Know About MOSFET driving (But Were Afraid to Ask) guide: https://reipooom.files.wordpress.com/2011/08/mosfet-must-read-2-slup169.pdf

The applicable simplest solution is fig. 19 for 3dgeo’s case, given the seldom on/off no PWM scenario.

You mean something like this (R1=R2=5K)?

That will work for DC, but it's too slow for PWM.

[dobsonr741]

PWM is not required, it would be nice feature and I'll probably implement Zero999 circuit just to see and test how it works.

Pump is not intended to be PWMed, but I've added flyback diodes on LED and Pump screw terminals just in case.

Great, no PWM simplifies.
R1+R2 = 5K is reasonable, should divide 24V not to exceed the MOSFET's max Vgs specs, and be enough to drive the few into saturation at the desired current.

[3dgeo]

Will these transistors do?

Is there any notes on how much resistance R1/R2 shoul have (while maintaining ratio)? For example 10k and 43K or 100K and 430K instead of 1k and 4k3? What impact that would make on Pfet gate?


P.S. dobsonr741 – Pfets: HSBB3103

[Zero999]

Will these transistors do?

They'll do.

Is there any notes on how much resistance R1/R2 shoul have (while maintaining ratio)? For example 10k and 43K or 100K and 430K instead of 1k and 4k3? What impact that would make on Pfet gate?


P.S. dobsonr741 – Pfets: HSBB3103

Higher resistor values will result in slower switching, but lower current consumption. The resistance seen by the MOSFET is roughly the value of R2 in my circuit divided by the h_FE of Q2 and Q3 in my circuit.

[dobsonr741]

The MOSFET is a bit low spec'd in Vds breakdown. You supply is 24V, the MOSFET is at 30V. Given its CH origin, I'd build in more safety. More like a 60V type.

R1, R2 = 3.3K will dissipate 43mW each when turned on, not a big drama.

[3dgeo]

Higher resistor values will result in slower switching, but lower current consumption. The resistance seen by the MOSFET is roughly the value of R2 in my circuit divided by the h_FE of Q2 and Q3 in my circuit.

So if I understand it correctly – wasted current (~4.5mA with 1k and 4k3)via Q1 (in your picture) vs rise/fall time?

The MOSFET is a bit low spec'd in Vds breakdown. You supply is 24V, the MOSFET is at 30V. Given its CH origin, I'd build in more safety. More like a 60V type.

R1, R2 = 3.3K will dissipate 43mW each when turned on, not a big drama.

I see your point, but I like small package and price, I will look for replacement if there will be issues.
As I've said I do not expect spikes from pump, adding diodes on output anyway, will be using quality PSU and have 100u power cap, also regulator is rated up to 28V so it will die first 

This is only a test board, I might even go for 12V PSU cuz it turns out 24V makes entire board way more complex than needed...

[Zero999]

Higher resistor values will result in slower switching, but lower current consumption. The resistance seen by the MOSFET is roughly the value of R2 in my circuit divided by the h_FE of Q2 and Q3 in my circuit.

So if I understand it correctly – wasted current (~4.5mA with 1k and 4k3)via Q1 (in your picture) vs rise/fall time?

Not quite.

Q1 forms a current sink. The current is determined purely by the value of R1 and the base voltage, V2 in this case. Here's a plot showing the current is constant, as R2 is changed. Obviously there's a limit, as the current will fall once the voltage across it exceeds that of R1, by Q1's saturation voltage.

[3dgeo]

I've updated shematics, now it looks like image below.
What will happen if power supply voltage changes, 12V instead of 24V?




As with new driving circuit there is no need to keep 12V or 5V rail I've changed buck regulator to spit out 3V3 and removed LDO.
One place I still need 5V is laser PWM output (high impedance input). If I want to change PSU voltage voltage divider is not a good choice, so I came up with circuit below (R9 purpose is to let user control upper PWM voltage). PWM will be up to 100KHz, Opamp – LM321.
Also in a same image I've added buzzer driving circuit, as Q4 was not suited in gate driving circuit I want to make sure I'm not missing something in this one.
Plese let me know if there are any issues with these two circuits, thank you.

[Zero999]

I've updated shematics, now it looks like image below.
What will happen if power supply voltage changes, 12V instead of 24V?

You've got the resistor values backwards.

If the voltage is reduced to 12V, the MOSFET gate drive will be reduced. Remember the shifting transistor acts as a current sink, which will fall out of regulation, once the supply voltage drops too low.

As with new driving circuit there is no need to keep 12V or 5V rail I've changed buck regulator to spit out 3V3 and removed LDO.
One place I still need 5V is laser PWM output (high impedance input). If I want to change PSU voltage voltage divider is not a good choice, so I came up with circuit below (R9 purpose is to let user control upper PWM voltage). PWM will be up to 100KHz, Opamp – LM321.
Also in a same image I've added buzzer driving circuit, as Q4 was not suited in gate driving circuit I want to make sure I'm not missing something in this one.
Plese let me know if there are any issues with these two circuits, thank you.

The LM321 is no good for 100kHz. If it's just a squarewave, there's no need for an op-amp. You're better off going back to the 5V supply and using a 74HCT gate to get 5V from the 3.3V output.