Non-obvious mosfet failure cause

[jwet]

Forrest,
Here's a good app note on hot swaps that you might find good reading.  One of the key features of these parts is a current limit with a delay and short circuit delay.  The only way to tell the difference between a normal insertion and a short on insertion is to wait a little while and see if the "short" starts to charge up.  Paradoxically, a large capacitive load is worse than a dead short- learned (or relearned?) something.  I think you have the right culprit.  Great board here.

ADI App Note-
https://www.analog.com/en/analog-dialogue/articles/understanding-hot-swap.html

[forrestc]

Physics says you'll dissipate at least (CV^2)/2 charging the cap from zero to V volts.. How and where that energy gets dissipated relates to the switch characteristics, the source impedance, the capacitor ESR and the impedance from the switch to the cap. Also the switch will incur additional dissipation from the gate drive losses, and the gate driver. Switch thermal impedances from the die to ambient, as well as switch die thermal transient effects will determine how the die temperature behaves during switching.
....
Seems if one can increase the source/line impedance and/or slow the switch turn on time to have a slower cap charging time this is a good path to follow if allowed.

This all sounds consistent with what I'm thinking.

In the capacitor charging case, what I suspect is happening is that the mosfet is turning on slow enough that the mosfet is where most of that energy is being dissipated and the time period is too short for it to be able to dissipate out of the die.   

I either need to be able to more aggressively turn on the mosfet, so that the energy loss is in the rest of the circuit, OR I need to turn it on much slower than I am, which may cause other problems.   I'm also considering whether I can insert an analog current limiter circuit around the mosfet in some way in order to ensure it never exceeds the maximum power dissipation under any circumstances.

[forrestc]

Forrest,
Here's a good app note on hot swaps that you might find good reading.  One of the key features of these parts is a current limit with a delay and short circuit delay.  The only way to tell the difference between a normal insertion and a short on insertion is to wait a little while and see if the "short" starts to charge up.  Paradoxically, a large capacitive load is worse than a dead short- learned (or relearned?) something.  I think you have the right culprit.  Great board here.

ADI App Note-
https://www.analog.com/en/analog-dialogue/articles/understanding-hot-swap.html

I'll review the doc as it sounds interesting and might help this out.

A lot of the problems I run into anymore is when my mental model of a part isn't complex enough to explain some subtle behavior.  In this case, I've always been able to largely ignore the turnon period as I'm getting these things into the "mostly conductive" zone quick enough that the dissipation isn't enough to cause issues.   Apparently I've been lucky with the slower turnon but needed to add that whole thought process to the MOSFET model in my head. 

It's interesting sometimes to review designs I did 20 years ago and see things I would never ever ever do nowadays.  Or be able to see the exact cause of a problem we were fighting back then which we never quite figured out.

[jwet]

The other thing that has changed over the years is the "specific Ron"- Ron per unit area of modern processes is much denser.  It used to be that a 10 milliohm FET was a bunch of die in a TO-220, etc., in these new super processes, the die areas can be tiny and the thermal mass is zero.  At least your package has a low theta.  Those SOA curves that everyone first jumps to first don't tell the whole story either- they assume you're fully enhanced.  You have to do a transient analysis like Bob did with Vds x Id while slewing into conduction or out.  The capacitive case has approximately twice the area under the curve.  Great problem.

[T3sl4co1l]

Well, a few things at once -- the die was never big for energy handling by itself, and that's over in a hundred microseconds or so.  By a few ms, heat is flowing into the copper tab, and it matters whether it's a weedy little SMT (I don't know the dimensions, but I'm guessing this is at least in part why SOT-89 always has such feeble ratings, despite what you'd think of its direct mounted tab design, in contrast to SOT-223's long gull-wing tab) or a thick plate as in TO-220AB (not the minimal garden-variety TO-220, mind you!) or the like.  Then in the 10-100 ms range, heat flows out of that tab into the heatsink (if any), and in the 1-100s range, heat spreads across the heatsink itself.

A small SMT like this, will never have much energy or power capacity, regardless of the process node used for its chip; even up to DPAK will be only a little bit better, still having a fairly thin tab.  D2PAK and power (THT) devices are where you need to go for energy handling at modest time scales.

Again, this is all filtered through the Rds(on) and speed vs. energy dissipation over time situation, so you might have a very small but low-Rds(on) part which, when switched quickly, seems more robust than a much beefier part; or if switched at an unfortunate enough (slowish) rate, performs about as poorly as you'd expect given its diminutive size.  So, without controlling for those variables, things that are all happening in well less than a blink of an eye -- it can seem random which ones are robust or not.

Not to even mention 2nd breakdown, which is hit or miss with modern devices.  Some are quite severely limited, others are shockingly wide despite their high power density.

Also just to clarify, sub-200V or so transistors aren't doing anything *too* crazy, like SuperJunction stuff.  They're just very highly optimized trench VDMOS or whatever.  Or maybe there are specific techniques applicable there that I've not read about yet, not sure.  SJ is coming to lower and lower voltage ratings, though: the tinner they can make the SJ pillars, the lower it's useful to.  They started at 600V I think (also the most lucrative and important market segment to improve with it), and are now down to 200V or so.  Sub 100V may be coming yet.

I wonder if they would ever use (or if it can be used at all) SJ on LDMOS (lateral RF) parts, heh.  Have seen a couple articles about charge-compensated lateral structures, seems possible.  Maybe not as advantageous as it is for power switching.  Shouldn't be any particular advantage with voltage, I think; you're still limited by drift through the channel (regardless of how it's doped), reducing performance above 100V or so.

Tim

[jwet]

All good points- agreed.  During my 40 or so years in the industry, I've seen device performance driven by the dominant applications. (I was an apps engineer basically...). There is generally some kind of theoretical asymptote dotted line line that shows up on all the figure of merit graphs that just keeps getting closer.

In the late 80's, 90's, computers- NB, PC's and servers and dense rack stuff needed hefty LV point of load supplies-  this drove Rons for small efficient DC-DC's.  This wasn't moore's law or anything, just some judicious engineering pushing and tailoring to the market.  Power MOSFET's in the 20-30V category improved a lot in that decade- Siliconix and Vishay.

Later, a lot of work was done on SJ and related vertical structures for med. current line voltage stuff like white goods, appliance motor drivers, etc.  Trading Silicon for copper and iron in motors, etc. improving efficiencies and lower cost.

Medium voltage, high current apps for automotive and battery power tools drove a lot of innovation for a while.  Electric vehicle needs seem to be pushing hard these days.  There are some clever IGBT/SJ like hybrid devices starting to show up.

SJ LDMOS sounds pretty cool, I'd have to talk to a real process guy.  As the application needs develop, I'm sure there are plenty of smart process guys/companies that will make it happen if there is a need.

At Maxim, the research and process guys were reading papers and thinking about different optimizations kind of waiting for design and apps to come calling.  It always seemed like when we asked, they could make a 5x improvement in any specific parameter by optimizing and sometimes trading somethings else off.

I don't follow this stuff closely these days but find it fascinating.