Non-obvious mosfet failure cause

[forrestc]

I'm hoping someone can point me to a resource to help me out of the "I don't understand how this could be failing" rut I'm in.   Note that this is a problem I sat aside for a couple months but need to pick it back up.  So I need to figure out which tests I need to do from here and adjust a test PCB layout accordingly.

I have an application where I tie two N channel mosfets (in the same package) together back to back - that is tie the gate and source of both together and then use the resulting circuit as a bidirectional switch to turn on and off DC of unknown polarity.  Think "AC" solid state relay but used for DC.

The gates are driven by a single photodiode output optocoupler (TLP3906) across the gate and source so the drive circuit is isolated from the mosfet.

After a supply-chain forced part change, I was having failures of this arrangement where the mosfet will turn on and will never turn off.   The failure results in one or both of the mosfets being shorted out.   Not sure if the failure occurs during turn on or turn off, but I believe it is likely during turn-on but I can't be sure.   I can reliably cause this failure by putting a relatively large (2000uF) cap across the output with a reasonable bleeder resistor across the capacitor.  I've seen this failure in various mosfets, but the SQJB80EP-T1_GE3 is known to easily exhibit this issue, whereas the original mosfet (SQJ974EP) did not show this issue.   Note that I've tried various mosfets after discovering this issue and some fail reliably and some do not.   There doesn't seem to be any parameter that I'm looking at (Rds(on), Vds(max), Vgs(max), Id, Vgs(th), etc), that predicts the failure.

Now, here's where the unknown/non-obvious issue comes from:

In an attempt to understand/prevent this issue I've:

1) Added fast "zener/tvss" diodes around the FET - (i.e. to protect from Vgs and Vds spikes), soldered directly across the part pins.
2) Added gate resistors and/or capacitors to slow turnon and turnoff (in case it was a surge current)
3) measured (with a scope and 70Mhz differential probe) the voltages across the device during switchon/off to verify ratings were not exceeded.
4) measured peak current (using shunt resistor) through the circuit to verify that Id and Idm wasn't exceed. 

With the caveat that 3) and 4) were bandwidth limited by the probe, I did not see a single measurement which explains why these should be failing.   The Voltages are never exceeded, at least external to the die, and the peak currents seem to be within limits.   

Note that this is a single turn on and then attempted turn off event, and not a PWM or any other pulsed event that causes this.  Also, these failures can be induced on the first switch of a brand new part so it isn't wear-out.

I believe what I might be seeing are internal di/dt or dv/dt failures or some other similar on-die interactions.   I've read various discussions about these failures, but I'm struggling to see how the circuit described is likely to cause any of the failure modes that are discussed in the various documents.   Especially with a primarily capacitive load. 

As an example, a Toshiba app note describes dv/dt failures at turnoff, but these all seem to be related to situations where the Vds would drop rapidly such as when driving a inductive load or in a very high speed hbridge application.   Other documents describe similar failures, but none seem to be able to be applied to my circumstances.

Any ideas here?

[Wolfram]

A potential candidate is junction over temperature caused by dissipation during the capacitor charging. As much energy ends up dissipated in the MOSFET as ends up stored in the capacitor, independent of how fast it turns on. You have to look at the precharge duration and transient thermal impedance for that time scale to figure out if it's fine.

The mentioned part has an Idm of some 80 A for 300 us, or 24 mC. This is enough to charge 2000 uF to 12 V. What is your supply voltage?

[forrestc]

 

A potential candidate is junction over temperature caused by dissipation during the capacitor charging. As much energy ends up dissipated in the MOSFET as ends up stored in the capacitor, independent of how fast it turns on. You have to look at the precharge duration and transient thermal impedance for that time scale to figure out if it's fine.

The mentioned part has an Idm of some 80 A for 300 us, or 24 mC. This is enough to charge 2000 uF to 12 V. What is your supply voltage?

I'll have to rattle this around in my head a bit mainly because I need to understand this principle better since I want to make sure I understand this before fully discounting it.  It's either 24 or 48V typically, so on the face, that's a possibility that this is the issue.   Going to have to do more research about how the heat gets dissipated over time.

However, I sort of ruled this out for the following the reasons:

The part which doesn't fail (SQJ974EP) has a lower Idm rating (65A), and so does it's successful replacement (SQJ980, 68A).    In fact the SQJB80EP is a better part than the SQJ974 and SQJ980 in almost every way (higher Id, higher Idm, lower Rds(on)).   The Vds is lower than the original SQJ974, but higher than the SQJ980 which doesn't fail.   Admittedly the lower Rds(on) may account for a higher peak current into a capacitor.

Oddly I have other alternative parts with higher and lower Idm ratings and also higher and lower Rds(on) which failed testing.

I also added enough r/c network at the gate to slow the turnon to the point where the drain current never exceeded the Id rating and still got failures.

[jonpaul]

VHF, UHF parasitic oscillatons between the two FETS.

Use single ended Probe and scope BW 200..500 MHz

Jon

[Wolfram]

48 V and 2000 uF is 96 mc of charge, if you limit the current to be constant within the Icm of the part, then the pulse would last for just over a millisecond. The part is specified for 300 us at Icm, with an ambient temperature of 25 C and a maximum junction temperature of 175 C. If Icm is thermally defined, which is not unrealistic, this corresponds to 150 degrees delta T at 300 us, it's left up to the imagination what happens if the pulse is extended to 1200 us. Temperature rise won't be linear for a given dissipation, given that the heat has time to spread out the longer the pulse is, but this still suggests that in case I_inrush is limited to be just within Icm, then you will massively overheat the MOSFET when charging 2000 uF from 48 V.
 
Which MOSFETs fail and which ones survive under these conditions is hard to generalize from datasheet ratings. Instantaneous failure usually means your junction is a lot hotter than the maximum temperature, possibly in the 350 - 500 degree range. It's impossible to say whether a MOSFET with an Icm rating of 60 A will always fail before one with an Icm rating of 80 A, because that's not what the Icm rating means.

Extending the pulse helps, but not linearly. The energy deposited in the MOSFET doesn't change with pulse length, it's fundamentally always the same energy that ends up in the capacitor (U^2*C/2 = 2.30 J at 48 V). If the load draws any current during the precharge event, then the energy dissipation in the MOSFET actually increases with longer pulses. Extending the pulse lowers the peak dissipation, which lowers the delta-t, but the device transient thermal impedance is also higher for longer pulses.

As an example, let's say you extend the precharge to 10 ms, and the power dissipated in the MOSFET is constant (it's easier to correct for this afterwards rather than doing the full calculation), then the power dissipated during the event is 2.3J / 10 ms = 230 W. Transient thermal impedance for the SQJB80EP for a 10 ms single pulse is 0.65 k/W, giving a temperature rise of 150 degrees, marginal given the fact that ambient could be higher than 25 degrees and the fact that dissipation during precharge is not constant. This would suggest that you need to extend the precharge time into the hundreds of milliseconds to have sufficient margins, or ideally chose a part in a larger package.

Id and Idm are just simplified limits with a lot of assumptions. In an application like this, the main thing to look at is the junction temperature against Tj_max. Simulation can be a valuable tool here, especially if you can find a device model that includes thermal dynamics.

[thm_w]

Have a similar issue and I wouldn't be surprised if its the same cause:
- 2200uF output capacitor
- 24V supply

SQJB80EP is rated at 0.019 ohm rds on at 10V. What shunt resistor value did you use? I assume from what you are saying the FETs still failed with the shunt in place.

I also added enough r/c network at the gate to slow the turnon to the point where the drain current never exceeded the Id rating and still got failures.

What specific Id value are we talking here, was it within the SOA listed on page 5 of the datasheet?


I would recommend uploading your gate and output voltage oscilloscope screenshots, if you have some.

[mawyatt]

A potential candidate is junction over temperature caused by dissipation during the capacitor charging. As much energy ends up dissipated in the MOSFET as ends up stored in the capacitor, independent of how fast it turns on. You have to look at the precharge duration and transient thermal impedance for that time scale to figure out if it's fine.

The mentioned part has an Idm of some 80 A for 300 us, or 24 mC. This is enough to charge 2000 uF to 12 V. What is your supply voltage?

Very important point that many don't seem to grasp!!

Best,

[wraper]

A potential candidate is junction over temperature caused by dissipation during the capacitor charging. As much energy ends up dissipated in the MOSFET as ends up stored in the capacitor, independent of how fast it turns on. You have to look at the precharge duration and transient thermal impedance for that time scale to figure out if it's fine.

Not really. Only if MOSFET is placed into an ideal circuit. If for example ESR of capacitor is the same as MOSFET channel resistance and it turns on instantly, then MOSFET would dissipate only a half of total energy that gets stored in the capacitor, the other half would be dissipated by the capacitor itself. But then also comes resistance of wires and power source which will dissipate their share of the energy.

[Wolfram]

Fair point, some of the charging energy will end up dissipated in the capacitor ESR. The total energy dissipated in any circuit resistance is equal to the energy stored in the capacitance and part of this ends up in the capacitor ESR, distributed by the ratio of the resistances including source resistance and capacitor ESR. I'm assuming all other resistances in the circuit are zero, which gives a worst case estimate, and some added margin in real world conditions.

I looked up some relevant parts to quantify the effect, and used the Nichicon UPS series as a reference, the 2200 uF 63   part has an ESR of 32 mohm. Assuming that the charging would be on the 10 ms time scale, the current is in the range of 10 A, and the voltage dropped across the capacitor ESR is 3 V, so 6 % of the total energy ends up in the capacitor. The effect is more dramatic for shorter charging times, and at the shortest possible charging time the share is approximately equal between the capacitor ESR and the MOSFET RDSon considering how RDSon changes with current. This reduces the temperature rise from around 600 degrees down to 300 degrees in the case of using this capacitor, and it could still be worse given that this is a random capacitor sample and ESR is a typical rather than worst-case value. So I agree fully with your point but I don't think it changes the conclusion.

[boB]

The TLP3906  is good for a minimum of 20 microamps to charge the gate of that very small mosfet die.

What I would be afraid of is that the gate is turning on SO slow that it is linear when going through the threshold and miller plateau and burning up because of power dissipation.  I don't know what the voltage across the FET's D-S.

Also, 7V maximum from that opto is not all that much to guarantee a low enough Rds-On with such a small die.  3 degrees C/watt thermal resistance Junction to Case is teeny-tiny.

You could try spicing the circuit with a MOSFET of a similar characteristics, if not THE same, and a 20 microamp current source limited to 7 V and see the dissipation or energy dissipated during the turn-on time.

IF you really want to use an OPTO something like this, I would maybe use 2 in series but at least make a circuit that charges up a cap slowly that can turn that FET on much faster when it charges to 6 or 7 volts.

boB

[T3sl4co1l]

This sounds like the wrong part/method for the application.

Tell us more about your source and load:
- voltage range
- available current or source impedance or characteristics
- load current range (vs. voltage, and time if applicable)
- load capacitance or inrush characteristics

And application:
- Required rise/fall time
- On/off ratio, allowable reactance (capacitance or etc.; notice Coss is large near 0V), or required voltage rate when off
- Min/max ambient temperature
- Allowed size, dissipation, cost

If you're running into SOA problems / overload characteristics, and reliability/robustness issues, you should probably consider a limiter type device, like a precharge circuit, load switch, protected MOSFET, eFuse, etc.  If several of the above parameters are looking particularly marginal with respect to available MOSFETs, you may well be better off with a good old fashioned mechanical contact.

Tim

[mawyatt]

A potential candidate is junction over temperature caused by dissipation during the capacitor charging. As much energy ends up dissipated in the MOSFET as ends up stored in the capacitor, independent of how fast it turns on. You have to look at the precharge duration and transient thermal impedance for that time scale to figure out if it's fine.

Not really. Only if MOSFET is placed into an ideal circuit. If for example ESR of capacitor is the same as MOSFET channel resistance and it turns on instantly, then MOSFET would dissipate only a half of total energy that gets stored in the capacitor, the other half would be dissipated by the capacitor itself. But then also comes resistance of wires and power source which will dissipate their share of the energy.

Obviously this was in reference to the ideal case, with only MOSFET Rdson as resistance.

However, the same capacitor energy is lost regardless of the MOSFET Rdson, switching time, source impedance, capacitor ESR, wiring resistance or anything else. The capacitor final energy is lost even with no resistance, as the source must deliver exactly twice that energy regardless of any resistances!!

Some analysis will show such, or a simple experiment with a pair of identical quality (film) capacitors.

Take one cap C1 and charge to V, other cap C2 has 0 volts, connect a DMM (use Hi Z State) across charged cap C1, disconnect charged cap C1 from charging source then short other cap C2 across charged cap C1 and note DMM reading, should be half the initial charged voltage as expected. Now both caps are charged to half the initial voltage, or V/2.

At start Cap energy = (C1Vi^2)2, where Vi is initial voltage.

Final Cap energy = (C1Vf^2)/2 + (C2Vf^2)/2), where Vf is final voltage on both caps.

Ratio Final Total Cap Energy to Initial Energy, or (Final EnergyC1 + Final EnergyC2)/(Initial EnergyC1), or  [(C1Vf^2)/2 + (C2Vf^2)/2]/[(C1Vi^2)/2]

With C1 = C2, the ratio is 2(Vf/Vi)^2, or 1/2!!

So half the initial energy is lost in this process even though no resistance was included.

Just for fun we got a couple quality PolyPropylene caps.

C1 = 4.84807uF ESR 0.00503 ohms
C2 = 4.84523uF ESR 0.00521 ohms

Charged C1 to 10.0002 Volts, C2 was 0 volts

C2 Shorted to C1 and Voltage was 5.002 Volts on DMM Hi Z mode.

Did same test with a 10K resistor in series with C2 and got the same result, as with 1K and 100 ohms.

This shows the switching resistance doesn't matter wrt to the energy lost, sure it can be dissipated in different places and begs the question what about absolute zero switching resistance...where does the energy go, radiating magnetic fields

BTW this understanding led us to a solution back in ~80 to a CCD clock driver problem driving a bunch of high capacitance CCD clocks lines at high rates and over 15VPP. The usual solution back then was a massive clock driver which dissipated very high power, we came up with a driver based upon a technique we called "Reactive Clock" to exchange the CCD clock capacitive energy with the supply and saved over 95% of the driver power!! Published in EDN much later when we were allowed.

Edit: Forgot to mention, you can use unequal capacitors for C1 and C2, then:

Vf =Vi(C1/(C1 + C2))

Best,

[mawyatt]

This would be an interesting research topic if one had accurate 1st and 2nd order thermal models including dynamics for the DUT. A study of the actual die transient temperatures wrt to driving waveforms, device characteristics, ambient conditions, bias, loads and such would prove very beneficial to the designer.

Maybe some grad student will pick up on this for a dissertation

Best,

[jwet]

+1 for Bob's theory.  These little solar cell opto's create really terrible current outputs.  Have you watched the Vgs during rising and falling.  I would expect a lot of class A type current in that FET with 20 uA Ig

[boB]

I did a quick LTspice simulation using a mosfet that is similar in gate charge, RdsOn at the gate voltage you are giving it and also, 80V Vds rating.

The gate charge of a  SQJ974EP  is 15 nC but that is for a bit higher voltage than 7V and of course it is a single part and you are driving two parts so this should be in the ball park.

The SQJ974EP data sheet calls out  a maximum single pulse energy of 25 mJ.   Using 24V to charge a 2000 microfarad cap (I added 30 mill-Ohms R) gives not quite  20 times that pulse energy limitation.

Looks like using a small current like this is not going to turn that FET on fast enough to keep it from turning into slag.

boB

[forrestc]

Thanks to everyone who has replied so far... I need some time for this to rattle around my head a bit, as I'm becoming convinced that this might be an issue of excessive heat buildup during the turn-on stage.   I'll probably do some testing here to verify.

Just to let everyone know, this is switching up to a 2A load @48VDC, the excessive current rating is to handle short-term overloads while fully on.   Part of the on-bench testing of this before we qualify a part (or before we ship updated firmware) is repeated short-circuits while on, and also turning on the FET with a short-circuit attached.   The rest of the picture here is that we do software overload protection with an current sensor to detect a short circuit and turn them off within a few ms.   All of the parts, including the SQJB80 pass this test with no failures.   That is, the software is able to detect and shut down the SQJB80 fast enough that it can survive repeated shorted outputs, either before or after turning on without issue.   This isn't a one or two shorts test, this is a leave it running with repeated short circuits every 30 seconds or so over several hours test.   

We warranty every product for a very long time and against almost every failure cause so we generally see most failures back.   We've shipped tens of thousands of copies of this particular circuit in various forms through the last 5 years with only a half dozen or so failures of just the FET, and they were all with the SQJB80.   Which is what was puzzling.   They also started coming back fairly quickly which was good so there weren't many copies out there with these in them.

We also lucked out and figured out that all of the failures was a result of a specific type of equipment that we discovered had an unexpectedly high inrush current, which is what led us here.   Switching away from the SQJB80 has resulted in the return rate going back to zero, but I'm not one to leave an unexplained failure alone since they'll often come back to bite me. 

Note that the vast majority of these products are powered with a relatively current limited supply in the field.  The largest we'd expect to see is 10A @ 48VDC, usually with foldback current protection.   The bench supply we would have been testing them with would be a LHP 60-18 set to 48VDC and a 10A current limit.   That isn't to say that we weren't getting more than 10A for brief periods while the charge from the supply output capacitors were being transferred to the "test capacitor".

I suspect most of you are correct in suggesting this is a "microscopic term" overheating issue, in that the fet melts before it can get rid of the heat generated on-die during the turn-on period.   I was focusing on not exceeding Id or Idm(300uS) or Vgs or Vds and not paying attention to the on-die heating which I've typically thought of as a more long-term problem (Rds(on)@4.5V x expected current) since this isn't a high speed switching application.

My only skepticism here has to do with my recollection of some of the tests we did that I'm guessing might have eliminated this type of failure as a cause, but my recollection is fuzzy enough (and my notes aren't helpful either) that I don't know for sure.  I'm also puzzled by the reliable passing of the "power on with a short circuit" test which one would normally expect to be the worst-case scenario, but obviously it isn't in this case. 

My purpose in posting here was to come up with a plausible explanation and then be able to come up with a test scenario to verify it.   So, my plan is to get a small test PCB fabricated which will allow me to more reliably probe around the FET and provide various drive options so that I can experiment with this further.    I'm also going to add some options for a more direct drive current for the base from a high current source to see if a very quick switch of the FET will make the failure go away. 

I really do appreciate everyone's posts did help me get out of the "what number on the datasheet am I violating" rut and thinking about the thermal behavior during that short turnon period.

[mawyatt]

If you have any of the failed MOSFETs, might be worthwhile for some post failure analysis.

We would offer to image the failed MOSFET die, but would have to unbox all the necessary equipment which is in storage. You might approach member noopy about this, he's got everything already in place, and does outstanding work! Of course the proper professional approach would pay for this effort as it's very involved, we know as we've been doing chip imaging for a couple decades and it takes specialized equipment, lots of skill, and quite a bit of overall effort to realize quality chip images worthy of failure analysis. 

Best,

[T3sl4co1l]

What I would be afraid of is that the gate is turning on SO slow that it is linear when going through the threshold and miller plateau and burning up because of power dissipation.  I don't know what the voltage across the FET's D-S.

If the challenge is charging a capacitor, slow is better -- up to the limit of whatever static load is in parallel with that capacitor.

Or very fast, with very low Rds(on), to let ESR and stray inductance limit the current.  Like a mechanical contact (sans contact bounce).  This could be 100s of A though, and there's absolutely no way an opto like that reaches those speeds (100s ns?).  (An opto like that, into a capacitor, then a Schmitt trigger dumping the cap into the gate, however would be interesting.)

On that note, there are things like this,
https://www.ixysic.com/home/pdfs.nsf/www/CPC1596.pdf/$file/CPC1596.pdf
but, still not fast enough.  Also pretty pricey...

But if testing includes short circuit conditions, low dI/dt (low Ig(on)) is probably the way to go -- again, at least up to whatever dissipation limit before protection fires and it turns off.  There's a sweet spot depending on voltage, current, delay, and SOA.

forrestc: there shouldn't be anything a short circuit finds that inrush or other doesn't, but don't forget to test at maximum temperature, and don't forget to test inductive loads, in case the customer might have something like that connected as well.

Tim

[boB]

Tim, yes, slow turn on might be fine IF it is well controlled.    This turn on is not well controlled.

He could add a large resistor across the FET to pre-charge that 2000 uF capacitor and then the transient would be much easier on that FET.

I'm not even sure that desaturation protection would help this situation.

I'm pretty sure that in this case that the die temperature is going way too high.

He might try cracking open one of these failed packages and see if the die did indeed turn to slag or maybe the bond wires broke ?

The die size in these parts are extremely small.   I think he has been lucky with very few parts breaking.

Overcurrent turning the part off in a few milliseconds is more than likely way too slow in most situations.

boB

[T3sl4co1l]

Datasheets:
https://www.vishay.com/docs/78092/sqj974ep.pdf
https://www.vishay.com/docs/76245/sqjb80ep.pdf

Basically identical SOA, and notice SOA is at Tc=25C, an infinite heatsink.  In a typical board-level application (Ta=25C), even the 10ms curve will be lower, but especially the 100ms+ curves will continue to lower and lower power levels, whereas they're all (100ms+) bunched up in the same place for Tc=25C.

Notice also, for 10ms (Tc=25C), it's about 1A at 50V.  If the capacitor charges to full at this current and time (i.e., 1A * 10ms = 10mC, C = Q/V = 10mC/50V = 200uF), and Vgs happens to cross the ~1A range slowly (that is, Vgs such that Id ~ 1A), it will survive.

Vgs swing takes some ~100s us for those opto drivers, which is pretty slow, but it's not 10s of ms, and the capacitance is off by an order of magnitude regardless.  This is a pitiful transistor for what's expected of it, it would seem -- that is, if 2mF @ 48V is what's required to be able to survive, but even at a generous 10ms time scale, it's rated only a tenth of that.

For very slow gate drive (say, hovering at a few mA Id, for 100s of ms, or ~s even), larger capacitors can be charged -- power dissipation approaches the steady-state limit and arbitrarily large capacitors can be charged.  This is up to a limit of, if the load draws more power while starting up than the transistor can handle, it can never cross the halfway point (peak power point) and finish charging.  So, if the load is a capacitor alone, or a capacitor with large resistance, or a UVLO circuit that only engages once nominal voltage is reached (or better still: plus some delay thereafter),

Hence why I said there's a sweet spot inbetween.  How much power is required at the middle of that sweet spot, depends on load resistance and capacitance, and supply voltage.

The other case is if the switch is already on (I don't think it's been mentioned yet how/when it switches?), and a heavy/inrush/short load is applied.  Evidently these MOSFETs will dump the better part of 100A, and promptly blow up.  You would need a sensor response PLUS gate drive delay total under 100us to do that.  And you still need voltage clamping, give or take how inductive the load is (and, mind, even 200nH is notably inductive at this current and speed, and 4uH is enough to blow the transistor by avalanche energy alone, even if it could handle the current, which it cannot).

The easiest way to constrain fault current, I think, is a G-GND zener combined with a S-GND shunt resistor: as load current rises, source voltage lifts above GND, reducing Vgs(on).  (Note I use "GND" very locally here, meaning the common point between the FET pair.  You would, I think, have one shunt resistor for each MOSFET, gate drive common to the center-tap between them, and then cross-connected G1-S2 and G2-S1 zeners.)  But this also increases Rdd(on).  And for such small MOSFETs, it doesn't gain you much fault time -- getting above 100us even isn't enough for this type of gate drive.

Tim

[jwet]

I defined some hot swap contollers at Maxim and we ran into problems like this.  The hot swap controller has to charge all the bulk and bypass C of its board as its inserted.  Customers wanted kind of snappy DV/dt rises to keep all the logic from running in brownout too long.  We had to be mindful of shorts and use techniques like PWM to precharge the load C in an adapative way.  It took us a few iterations of these designs to get them right.  They also had kind of anemic gate charge sources provided by an on board charge pump using on IC caps, pretty tiny.  The other issue with hot swaps that may or may not apply was unplugging an adjacent card, it could cause a line input transient that the other hot swap controller working against their highly capacitive input could sense as a short on their own board.  The problem was that we didn't have much control of the environment of our own load c and the bus c and adjacent card c.  It might be fruitful to look at some app notes on hot swap controller from Maxim or LTC.  Its a bitchy problem.  Good disicussion.

[thm_w]

The other case is if the switch is already on (I don't think it's been mentioned yet how/when it switches?), and a heavy/inrush/short load is applied.  Evidently these MOSFETs will dump the better part of 100A, and promptly blow up.  You would need a sensor response PLUS gate drive delay total under 100us to do that.  And you still need voltage clamping, give or take how inductive the load is (and, mind, even 200nH is notably inductive at this current and speed, and 4uH is enough to blow the transistor by avalanche energy alone, even if it could handle the current, which it cannot).

OP is saying they already did a short to ground test, and it had no issues (short on power on and after).
But I can't see how a 2,000uF cap is worse than a short to ground in this scenario?

[T3sl4co1l]

OP is saying they already did a short to ground test, and it had no issues (short on power on and after).
But I can't see how a 2,000uF cap is worse than a short to ground in this scenario?

Yeah, dunno.  Would have to see some waveforms, of course how the original failures occurred (at customers) will remain a mystery.

Tim

[forrestc]

Ahhhh!!!   Ok, I might have a theory here. 

We have purposefully designed the upstream power network to these devices to provide a fair bit of impedance and to help limit the short circuit current.  The bulk fuse and the per-channel fuse is on the power supply side of the fet.  The power distribution net is intentionally sized for the expected load from the bus and so on, all with the idea that we wanted to help the FET survive and giving it infinite available Isc isn't a good way to accomplish that.  As a result of the designs,  Isc on the short circuit test we regularly do doesn't seem to exceed 15-20A. 

In a short circuit, most of the voltage is going to be burnt off by the power distribution net, and the Vds on the fet is going to be rather low.   I'm going to have to make some measurements to make sure, but I wouldn't be surprised if the Vds on a short is only 10V across the fet (or less) since there is going to be lots more resistance elsewhere.   After reviewing the datasheets and the code I realize that the turnoff time is somewhere under 1ms on a short, most of which will be opto delays, and not the longer period I mentioned before.   Just looking at the safe operating area on the fet for 10V and 25A puts us right at the 1ms line which of course isn't a good spot to be, but in many cases would be survivable.     So that explains why the short-circuit turnoff might be survivable always - it effectively lowers the Vds, thus lowering the energy being burnt off by the fet on a short circuit.   The turnon seems like it might be worse since there is some time spent charging the gate, but that's something I'm going to also spend some time simulating/measuring (but see below).

Because the capacitor doesn't trip the "this is a short, and we need to take immediate action" threshold, I wouldn't be surprised to see that we're well above the safe operating area for long enough for the FET to turn to slag.  Which would explain why the capacitor load might cause the failure but the short circuit doesn't.  It's creating a short term overcurrent not enough to trip the protection promptly but enough to cause a failure.

I'm also now noticing some stuff in the Dynamic section of the datasheet.   The SQJB80 seems to have the largest gate charge out of the bunch.  Ciss, Coss, and Crss is also higher at the voltage of interest.    I'm going to have to throw this into a simulator, but it seems like the SQJB80 is likely to spend quite a bit more time in that turnon region than the other two.   What I didn't do is add any gate drive resistors to a SQJ974 to see if slowing down turnon caused it to fail as well, so this might 100% be a it doesn't turn on fast enough issue on the SQJB80 vs the other two.   Admittedly I don't do a lot of high speed switching work, so I tend to have to do a lot of work anaylizing that portion of the datasheet when comparing parts.     But I could also see how we might be right at the edge here for a capacitive load and the SQJB80's slower turnon might just push us over the failure limit.

Ok, thanks everyone, looks like I might have a theory to test which matches the available data....   Looks like I need to better understand the amount of energy being dissipated by the fet during the turnon periods for each of these scenarios.

[mawyatt]

Physics says you'll dissipate at least (CV^2)/2 charging the cap from zero to V volts.. How and where that energy gets dissipated relates to the switch characteristics, the source impedance, the capacitor ESR and the impedance from the switch to the cap. Also the switch will incur additional dissipation from the gate drive losses, and the gate driver. Switch thermal impedances from the die to ambient, as well as switch die thermal transient effects will determine how the die temperature behaves during switching.

In extremes one can make the source impedance, or the impedance to the cap high and minimize the switch dissipation, or one can utilize a very slow turn on time so the switch dissipation gets spread over time and the die thermal transient peak reduces. Power is the rate of change of energy, so slowing the energy dissipation transient reduces the power.

Seems if one can increase the source/line impedance and/or slow the switch turn on time to have a slower cap charging time this is a good path to follow if allowed.

Best,