Oh no! Another Multislope ADC

[uliano]

Dears,

I've been reading the numerous conversations about this topic and I decided to give it a try. The purpose will be mostly learning, anything over 4 1/2 digits will be regarded as a success.

As I'm at rookie level I decided to do nothing fancy, but follow the lines in AoE for multislope III: read ADC, runup 7500 cycles at 375 kHz, read ADC, ...

I wanted to realize the freewheeling runup by exploiting the fancy silicon in the AVRxxxDA/DB, namely Events and LUTS. With an AVR128DA48 I missed by a tiny bit and an 7402 is needed (if I'm not hallucinating). The idea is to have the micro completely free during the runup and start ADC and rearm the next runup in an interrupt.

The free time can be used to do some math to get actual calibrated voltage and to send away results, initially on serial but then also with SPI.

Here is the first draft of the schematic capture, any comment, hint, criticism, is very welcome.

I will probably try to set some pieces up on a breadboard, meanwhile I'd like to prepare to spin a PCB as I feel that It will become clumsy very quick.

Most is taken from here and there, I hope there isn't anything dramatically stupid but an expert revision before finalizing the board will increase the chances of any success.

Input buffer is missing and I haven't decided yet how much of it to implement in this project (It is an ADC non a Voltmeter)

 AVR-MULTISLOPE.pdf (116.2 kB - downloaded 85 times.)


 

[free_electron]

Don't use 4053 ... you use precision stuff everywhere else and then you put in one of the worst analog muxes ...
look at the DG family from siliconix / vishay

You also can't switch the negative ref voltage like that. You need to tie the vee pin to a negative rail.
You are switching 10v and -10v from a device powered at 5v ... not going to work. the ESD diodes alone are going to clip the signal. Use jfets. study manuals from keithley multimeters like 1xx series

[macaba]

free_electron - how can you be so confidently wrong?

[free_electron]

free_electron - how can you be so confidently wrong?

If you feed +10 into the input of the 4053 it will be clipped through the esd diodes to the +5 rail. same for the -10v.

Now, he is using the balancing technique HP/Agilent uses where there is a summing point formed AFTER the 4053 (input of U12).
But that is not shown in his schematic. the Vbuffer signal has to be driven from an opamp.
So., ideally all those inputs sit at 0 volt ( or close) as the balancing point is the negative input of U12, which , ideally, sits at 0 volt

It works because this is a current mode system. Blatant rip-off of the systems used in E3631 power supplies for example

if you do not actively drive Vbuffer this system will not work. You can't just leave that signal floating. it needs to be hard driven. There is a difference between an open wire and driving a signal hard .
schematics are incomplete.

[uliano]

Funny thing! at Agilent (my primary source here) they didn’t know what they were doing back then. Luckily enough, no one snitched it to the DMMs that keep working flawlessly enough until now.

[uliano]

@free_electron, I know that it is missing the buffer, it is still a draft. I’m focusing on how to avoid cpld/fpga and still have freewheeling of the processor along runup.

[Kleinstein]

The 4053 type switches are OK. Compared to most of the higher voltage ones they are relatively fast. For higher speed (and less jitter) the LV4053 would be a small upgrade that fits the same pin-out (neg. supply not used).
As another advantage the on resistance is lower and thus less need to have the same resistance for the 3 switch paths.

For only a first test there is no need for LT5400 resistors. MORN or the SO8 size ORN series are well good enough.

For the reference part I would consider using +-14 V instead of +-10 V: this is easier and more stable for the gain with 2 equal resistors. The ADC anyway wants a relatively high ref. voltage as some of the +-Vref range is lost to the fixed part of the modulation cycle. The 34401 ADC uses a kinf of 100K+42 K divider for the input, which is not ideal noise wise.
To keep the effect of the TC of the switch on resistance low one would ideally have the same restance at the references and the input. So maybe 100 K to the input and 100 K to ground.

For the amplifiers at the reference OP07 or OPA202 are well good enough. The OPAx210 is super low voltage noise, but high current noise and thus not ideal with resistors > 2 K. Similar U14 could also be a more moderate type. One could probably get away without U14A (buffer at the integrator) and use a RR OP-amp with the 0/5 V supply for the difference amplifier before the ADC input. That is kind of a simple way to limit the output voltage.

The feedback part would likely need a comparator signal to the µC.

The decoupling capacitor C10 should be at the other side of R17.

The integrator should have a series RC element to ground at the input. This can help to reduce ringing.

For the oscillator I would prefer a ready made canned oscillator and no do your self - interference towards the oscillator can cause nasty INL.

[free_electron]

You need to have an opamp driving "Vbuffer" or the circuit will not work. Vbuffer cannot be a high-impedant node. There is a difference between 0V and "high impdant"

The guys at HP knew exactly what they were doing. The problem is this circuit only works when implemented correctly. If you look in the service manual of a E3631 supply you will see that they have an opamp driving the 4053.

I've repaired many boards with this circuit (E36xx series power supplies ). They die because some of the 30K resistors go open or change value. The resistors, the opamp and the comparator are weak points. it runs hot (AD706 / AD711). i wrote several lengthy posts here on eevblog in 2012 about this circuit.

In the multimeter they use a custom multiplexer IC with JFETs.

They play several tricks at once. (charge/discharge the integrator periodically to keep the summing point close to zero). To avoid driving the 4053 into the ESD diodes they switch the unused pathway deliberately to ground.
I've seen boards with fried 4053. During startup the processor takes time to come out of reset and slow to engage the mux. If one of the power rails conks out there is a risk the +5v digital doesn't start ( caused by a tantalum cap on the daughtercard, close to the heatsink). This causes a latch-up and the 4053 self destructs when the power rail eventually does come up. (leaving a nice crater in the middle of the chip).

They have another trick up their sleeve : the third channel of the 4053 apparently doesn't do anything. ( its control signal is hard tied to ground ). the reason is to minimize error due to the resistance in the channel. It's kind of funny as the inputs are fed through 30K resistors.... you'd think that 120-or-so ohm channel resistance would be irrelevant.

Maxim has an application note for an enhanced version of the 4053 : MAX4053A where they have a guaranteed channel-to-channel dispersion and they also show a circuit how to prevent the esd diodes to trip into the rail by adding two diodes. I used the MAX4053 in the range switching on ADSL modems.

The chip Agilent uses is a 74HC4053 from fairchild (older units used National semi until that division was spun off) which has a lower channel resistance than a normal 4053 ( 50 ohm vs 125 ohm)

[Kleinstein]

Even if the 4053 is not switched correctly the reference current (10 V and 30 K) is rather limited (320 µA) and would not cause a latch-up. With modern chips this takes usually more than 100 mA.
Too high a supply could be an issue with the 5 V derived from the main reference and possible overshoot.
In my ADC variant I have tested the max4053 and it did a bit worse than a normal HC4053 (from Ti).

The input should have an amplifier or buffer and likely a mux chip (like dg508 or mux508) in front to choose a voltage source or GND or the 7 V reference.

[iMo]

I would not go with that MCU, frankly. Perhaps you want to use its CCL, but do mind even the rpi2040 with its PIOs has not been "successful" in the multislope experiments some time back (you may find the thread here)..
Also with ADR1399 you want the 1u ser 5ohm snubber at its output, afaik..

[free_electron]

Even if the 4053 is not switched correctly the reference current (10 V and 30 K) is rather limited (320 µA) and would not cause a latch-up. With modern chips this takes usually more than 100 mA.
Too high a supply could be an issue with the 5 V derived from the main reference and possible overshoot.
In my ADC variant I have tested the max4053 and it did a bit worse than a normal HC4053 (from Ti).

The input should have an amplifier or buffer and likely a mux chip (like dg508 or mux508) in front to choose a voltage source or GND or the 7 V reference.

The negative voltage on an input ( with the VCC being off ) is enough to tickle the parasitic thyristor in the substrate. When the 5 volt rail then comes up and the thyristor now runs the full current available from that rail  close to an amp ).

The fault happened because a small tantalum on the 5v regulator (one of those Cherry brand regs that are clones of an lm2596) was shorted  both fuses on the +15/-15 were blown. i replaced them. power on -> this time the tantalum blew up so the 5v rail restored itself and the 4053 went kaboom. This was on a e3631a. The regulator sits on the top board . The +15 and -15 (and thus the reference and +10/-10) were up before the 5v came up.

i've repaired at least 20 of those supplies with various faults. If the converter fails : replace the AD706 AD711 , the 4053 and check that the resistors around there are ok. Those red resistors they used ( i don't know who makes those) tend to go open. Their electrodes corroded open.

[NNNI]

even the rpi2040 with its PIOs has not been "successful" in the multislope experiments some time back

I think this has more to do with the fact that I haven't found much time to continue working on the project than the capabilities of the microcontroller itself. I'm not the only one who has tried using the RP2040, another forum member has achieved 0.67 μV rms (1 NPLC integration time, if I remember correctly).

[Kleinstein]

The AVR128DA48 could work for the ADC control, but it looks a tight fit.
I don't know if the CCL part is sufficient - it may work.  It is still not easy with the limited resources (6 LUTs and 3 sequencers (flip flops)). The event system could control the µC internal ADC and maybe do the counting.

It would make sense to test this before getting real hardware. So write the basic code. If it may work check with simple hardware (e.g. breadboard, raster and the µC on a develelopement board). This could be lower clock and with a simple 1 OP-amp integrator and simple reference (e.g. use the supply and simple inverter) - just to see if the logic works, not for any performance.

If it works there is nothing wrong with using a µC, as it allows a really simple system. A CPLD or FPGA tends to need an external auxiliary ADC (if this is wanted) and availabilty in an easy to handle case can be more tricky than with µCs.

AFAIK the RP2040 version kind of worked and the issues were more on the analog side, the µC internal ADC and maybe with clock synchronization. Ideally one would want an extra step of synchronization behind the µC / CPLD / FPGA, as these can have quite some jitter.

[iMo]

2040 worked with runup (as that fit somehow in, as I can remember) and NNNI's version used ADC for the residual charge (none rundown). The rundown did not fit in the PIO (nor 2350 will help as its PIO looks to be the same, a pity)..

PS: the advantage could be the AVR128db64 is up to 5.5V Vcc, but 64pin flatpack as any small fpgas. Also I would use an external ADC.

[uliano]

Dears,

Thanks for the suggestions that will be incorporated in a next schematic version

@iMo, yes Its is the will to test how much can be done with events and luts, and also I don't like easy path and appreciate 8bitters when they can fit the purpose.

@kleinstein I will definitely test the lut+events machinery with a minimal integrator on a breadboard before spinning a pcb.
Any suggestion for op-amp parts is welcome as, you guessed, I'm not much into it (the parts were chosen partly by coping and partly by looking at drawers (but I can definitely buy more suitable parts). One thing I'm regarding as important is the variation of gain and offset with temperature.
Regarding the resistors I'm not sure to have understood all implications here, here thre is a 100k for the Vin and 50k for the V+ and V-, the choice has been done to have a quick enough effect on the charge, just imagine to have Vin = -10V if the resistor were equal I will never be able to equilibrate the integrator. Here there will be no pre discharge step, just adc after - adc before should give the charge balance.

@all I'm not sure to understand why here it is used a double throw that shorts to gnd the unused sources, if I could make it with ST switches I could save 3 nands and use the Inhibit* of the 4053 (or some DG part that have some switch NC and some NO so I can save also the inverter for driving V- and would have no logic parts outside the AVR which would make me really happy! :-)

Here attached is the plan on how to wire the inner silicon of the AVR. I apologize for the bad drawing mostly due to my sloppiness aggravated by flu shivering. hope it is clear enough. There were a few errors, I re uploaded a corrected versione

[Kleinstein]

The unused input currents are send to ground, so that the voltage at the resistor and switch stays nearly constant. This way the switch and parasitic capacitance gets less important. It is also a way to use the low voltage (e.g. 5 V supply) switches with a 10 V or more signal.

The inverter for one of the switch signals is no really needed: one could swap the NO/NC pins to get a similar effect.

The question is, if one actually need to disable all the channels ? for normal ADC operation (similar to the 34401) one would not need this. It could make some sense, if one wants to stop the integrator and this was have it easier to use the µC internal ADC with less timing constraints.

I don't think the runup- feedback is working well as planed. I see a very simpe pos/neg feedback pattern, but no extra fixed phase to get a fixed number of switching events.

[uliano]

"so that the voltage at the resistor and switch stays nearly constant."

now I see the reason for it, if I simply disconnect without current I get voltage at  V+/V- in sorta like a squarewave

"The question is, if one actually need to disable all the channels ?"

In my mind this is when I run the SH for the ADC, I want voltage  on the ADC input damn constant all along those 2 us.


" to get a fixed number of switching events."

There is no such a thing as a fixed number of switching events, here there is a fixed number of cycles, switching is decided by AC state when the rising clock front arrives.

And I think that it is reasonable, if Vin is far away from ground there will be many cycles with no switching until the AC crosses the 0, so longtime no switch.

Anyway, time for a breadboard I shall see if I can get both hardware and software be able to equilibrate the charge without micro actions.

[Kleinstein]

I can somewhat understand the idea of stopping the integrator, to read the residual charge. The question is if this needs external logic, or one could get this also with the internal logic.

Ideally one would have extra external FF to synchronize at least the reference part. Something like HC74 or HC175 type flip flops could also provide an off function via the reset input(s), if needed. One would however still need an inverter with a HC175 type FF. The input path at least would not need extra logic. Stopping the integration is kind of the only function of the switch.

The reference switching events can add some extra charge to the integrator. This is from the switch charge injection, but also the delays and capacitive coupling around the chip. This extra charge may also drift with temperature. So it would really help to keep the number of switching cycles constant. Essentially all serious MS ADCs do this to get good linearity. I think the limited internal logic could still be sufficient to also get this system:
One sequencer would act as a D FF for the comparator and an extra LUT would combine the comparator signal and 2 timer PWM signals (same timer but different PWM value) to the feedback pattern.
I still don't understant of the sequencer output could be used as input to another LUT.

[uliano]

" The question is if this needs external logic, or one could get this also with the internal logic."

my idea is this, when the modN expires the number of cycles an ISR is generated

here just the minimal housekeeping, detach inputs,  start adc rearm the modN counter and when the 2us for the SH are elapsed (this may need or not a delay depends on the length of the housekeeping, but we know in advance the number of clock cycles for each instruction so it is easy to figure out if a delay is needed and how long we should wait) and then, still from within the ISR re-enable the inputs and start mod N counting.

About charge injection at the moment it is a higher order effect, I will care about it if I get to a 4 1/2 digits at least.
I guess that having the count_positive and count_negative = counts - count_positive it should be possible to compensate for it.
Moreover the injection is not exactly constant as the voltage downstream the switch is not exactly constant but yes, this would be an even higher order effect.

There is needed another ISR to get end of conversion and store the adc result. but apart from that we have 20ms free time and some 5-10us busy. In the free time data can be processed for calibration constants and sent trough serial or SPI or I2C. This is interesting as, IF IT WORKS, different units can be used and coordinated by a master microcontroller.

This architecture (start the ADC and go with the runup) is easy to restart anytime after a common trigger so it could be feasibile to have e.g. simultaneous acquisition of voltage and current. Ok I'm dreaming :-)

"I still don't understant of the sequencer output could be used as input to another LUT."

This is the beauty of these little chips, you do a lot of thing through EVENTS. I still have many test to do but there is lot of flexibility in there. The chapters EVENTS and CCL of the datasheet are somewhat terse but my bet is that it would be feasible. But I need the breadboard first.

[Terry Bites]

Oops, I didnt see all of your pdf the first time, reader error!
I'm not at all qualified to make much of a comment, though I think DIY jfet switches are the way to go in ADC's of this type.
They have, of course, much lower leakage and charge injection. Also see.
www.eevblog.com/forum/projects/charge-injection-cancellation-on-jfets/

BTW. I recently read this old HP article on an 8.5 digit ADC.
Amazing for it's day.

[Kleinstein]

The extra switching effect (charge injection, delay etc.) would likely be a main limitation to the linearity. Probably still OK for 4.5 digits, but maybe not much more. A numerical correction could be tricky, as the number as there are different patterns that can give the same result. This is especially a new zero input with either a +-+-+- pattern or a ++--++-- type patters that can come up with only a little hysteresis. Even if the number of switchign events are known, one would still need to get the charge per event as extra parameter.

A constant number of switching events (e.g. like in the 34401 or LD120) could be a big improvement for the linearity.

The CCL system should be able to also generate such a pattern: one sequencer would latch the comparator and a LUT would than combine the 2 PWM channels with the comparator. Including the hold part could need a link via an IO pin as the LUT only link to n+1.

@Terry Bites:
no need to use JFET switches. They are quite some effort and the CMOS switches work fine.
One can use different switches, in cluding JFETs and diode current steering (e.g. use in the old HP3455).

[uliano]

there is no way with the logic I devised to have constant switch number as there is no pwm at all: switch happens sync with the adc_clock ONLY IF needed (Analog comparator decides)

[Kleinstein]

To get a constant number of switching events one would need some extra PWM kind function. So there are 3 phases like this:
1) a fixed positive reference
2) a fixed negative reference
3) the comparator dependent part
2 PWM signals with the same frequency and different PWM settings could be combined with the latched comparator signal in another LUT to generate the signal. The same timer could likely also provide the clock to latch the comparator, e.g. at the start or end of the 1st phase.

[uliano]

I’m not sure if the pwm swap can be fully driven only by events/luts. Anyway the description of multislope III in the AoE doesn’t mention PWM nor constant number of switches.

I think I’ll begin by implementing that and see if and how the charge injection can be accounted for by software.

The idea of constant number of switch assumes that the injection is constant across integrator voltage and by sign of the current switched. Under these hypotheses, software calibration seems manageable as the unbalance in number of positive injection vs number of negative injection is known exactly.

Also, the ability to balance the integrator by swithichin PWM betweew 80/20 to 20/80 or even 90/10 to 10/90 is greatly diminished with respect to my 100/0 to 0/100 non PWM pattern (now I see the reason for 14V)

[NNNI]

AoE 3 is not an exhaustive work about the topic of charge-balancing ADCs. A few more practical details can be found in this famous document: https://www.worldradiohistory.com/Archive-Company-Publications/HP-Journal/80s/HPJ-1989-04.pdf, you could consider this a proper "beginner's guide to multislope ADCs".