CPG196 ball grid array - don't try this at home?

[ebastler]

I am looking to design a small FPGA board which needs to fit into a DIP-40 socket. Initially thought I'd use an iCE40UP FPGA, but that turns out to be under-powered for my needs. So the Spartan-6 in its small CPG196 ball-grid array looks like a good choice. 8*8 mm² footprint -- but it comes with a somewhat intimidating, small-pitch BGA: 14*14 balls in a 0.5 mm pitch.

PCB manufacturing is the first hurdle: Xilinx recommends a 0.15 mm drill for the vias, while the low-cost PCB houses seem to use a minimum drill size of 0.2 mm. I guess that problem can be solved by going to a more expensive place... But how about populating the PCBs?

This is strictly a homebrew project, and I plan to hand-solder just a few of these. Is it a realisitic endeavour to try that, say with hot air from above and a pre-heating plate from below? Or would you say that the tolerances are too ambitious?

Thank you for your feedback or experiences with this type of package!

[PA0PBZ]

Probably not helpful at all, but when I read DIP-40 I remembered this: https://www.micro-nova.com/mercury

[cgroen]

I am looking to design a small FPGA board which needs to fit into a DIP-40 socket. Initially thought I'd use an iCE40UP FPGA, but that turns out to be under-powered for my needs. So the Spartan-6 in its small CPG196 ball-grid array looks like a good choice. 8*8 mm² footprint -- but it comes with a somewhat intimidating, small-pitch BGA: 14*14 balls in a 0.5 mm pitch.

PCB manufacturing is the first hurdle: Xilinx recommends a 0.15 mm drill for the vias, while the low-cost PCB houses seem to use a minimum drill size of 0.2 mm. I guess that problem can be solved by going to a more expensive place... But how about populating the PCBs?

This is strictly a homebrew project, and I plan to hand-solder just a few of these. Is it a realisitic endeavour to try that, say with hot air from above and a pre-heating plate from below? Or would you say that the tolerances are too ambitious?

Thank you for your feedback or experiences with this type of package!

I have soldered countless BGA's with 0.6mm pitch on a hotplate at home (reflowr), not a single hickup! PCB and stencils from JLCPCB (via holes was 0.2 however!)

[ebastler]

https://www.micro-nova.com/mercury

Neat, but those guys have made it a bit easier for themselves: That's a DIP-64 package (68000 size); it is wide enough to fit the TQG144 package. I don't have that room unfortunately.

I have soldered countless BGA's with 0.6mm pitch on a hotplate at home (reflowr), not a single hickup! PCB and stencils from JLCPCB (via holes was 0.2 however!)

Thank you, that's reassuring! I will start dabbling with the layout, and will check how 0.2 mm holes look in that crammed neighborhood of the 0.5 mm BGA pitch. Prices go up a lot if I really need 0.15 mm drills...

[cgroen]

https://www.micro-nova.com/mercury

Neat, but those guys have made it a bit easier for themselves: That's a DIP-64 package (68000 size); it is wide enough to fit the TQG144 package. I don't have that room unfortunately.

I have soldered countless BGA's with 0.6mm pitch on a hotplate at home (reflowr), not a single hickup! PCB and stencils from JLCPCB (via holes was 0.2 however!)

Thank you, that's reassuring! I will start dabbling with the layout, and will check how 0.2 mm holes look in that crammed neighborhood of the 0.5 mm BGA pitch. Prices go up a lot if I really need 0.15 mm drills...

One thing, I constantly violate JLCPCB rules of 0.2/0.45 via, I use 0.2/0.352 instead, they never complain, and the board works

EDIT: check here, details about my boards: https://www.eevblog.com/forum/microcontrollers/pcb-for-a-bga-microcontroller/msg3013184/#msg3013184

[T3sl4co1l]

Well, for one, consider SMT leads.  That keeps the top side open.

Consider some via-in-pad process.  If you're doing it by hand, it probably doesn't matter, put on enough solder paste and flux until it works.  Ideally, you want:
- Untented vias.  Gas can escape through the via, rather than trapping a bubble under the joint.  Will probably wick some solder, making questionable joints.
- Shut or capped vias: may be more expensive.  Does not trap gas, so is fine.
- Capped and plated vias: preferred, but expensive -- the capping process takes time and manual labor, and the overplating takes extra steps.
- HDI (high density interconnect): preferred.  Not expensive in quantity (cellphones are a huge user), but maybe not what you want for a few protos.

There may be other middle-grounds, like blind or buried vias.  A 4 layer stackup with 2 x 10 mil cores can be drilled for L1-L2 and L3-L4 vias, then glued up to make the final build.  (Or they still assemble it as normal and blind-drill before plating? I forget.)  Blind vias obviously still trap gas, but not as much as full-height tented vias, and maybe that's good enough.

Laser-drilled vias can be smaller than mech. drilled, and may end up plated shut (good).  Not sure how much cost differential that is, honestly.  But keep in mind, any discussion of cost difference is basically moot when you're talking a custom proto run in small quantity.  You can spend $500 easily.

You might need blind vias anyway, just to route things.  A full height via blocks everything on all layers, a real PITA for high density layouts.  I don't know if you'll need enough IOs that a 4 layer build is impossible, but you can easily need 6, 8 or more layers.

Keep this in perspective: those cheap $10 runs are mainstream, huge throughput, carefully optimized processes.  Every thing you do differently from that process, adds cost.  And not arithmetically, but geometrically.  A few things -- 2oz here, 1mm laminate there -- are common enough that they usually have optimized processes with little additional cost, but going to a custom stackup, precision drilling, capping, plating, all that stuff -- it goes up quickly.  On the upside, you're at least paying enough to get good quality and customer service (something you definitely aren't getting on $10 protos!).

Tim

[ebastler]

Thank you both for your further feedback, cgroen and T3sl4co1l!

I have played with the footprint and via diameters in Eagle a bit. Unfortunately it's pretty clear that Xilinx had a good reason to suggest 0.15 mm via drills, and 0.27 mm copper diameter for both, vias and pads. There simply isn't enough room for larger structures if one wants to preserve plausible clearances between the copper areas.

I guess I will switch to the next-larger BGA package Xilinx offers, the CSG225. At 13*13 mm² outer dimensions, it sits awkwardly tight between the pin headers of a DIP-40 size PCB, which I had hoped to avoid. But it comes with a much more comfortable 0.8 mm pitch, which means 0.25 mm recommended drill size for the vias. Phew...

As T3sl4co1l said -- getting to that smaller scale is probably straightforward if done in mass production. But I'd rather stay within charted territory for the amateur (and the cheap Chinese fab) here... Your layout hints in the other thread are really helpful, cgroen, I had overlooked that one!

[ale500]

There are QFN72 parts, for instance this MachXO3D:

https://www.mouser.de/ProductDetail/Lattice/LCMXO3D-9400ZC-2SG72C?qs=sGAEpiMZZMsG1k5vdNM%2FcywAWuSJICbqeprFtlBDAzc%3D

It costs like 17 € plus Mehrbiersteuer.

It has almost double the logic of the iCE part you mentioned but no multipliers. But more (and dual ported) block RAM. It may be an alternative in a bit nicer package.