ADCMP60* hysteresis pin

[aiju]

I'm quite confused why the ADCMP60* datasheets (e.g. [1]) claim there is an internal 70 k? resistance when that seems to be inconsistent with everything else in the datasheet.
The only reasonable interpretation of the 70 k? figure, that I can think of, is that the equivalent model* is a 1.25 V voltage source in series with 70 k? (i.e. basic Thevenin equivalent).
The hold mode activates around 1.1 V at the LE/HYS pin, so we don't want more than 0.15 V drop across the resistor. 70k? would limit the current out of the pin to 2?A which is an order of magnitude below the 25?A cited in the datasheet for maximum current out of the pin. There is tons more examples like this in the datasheet that make no sense given this equivalent model and the 70 k? figure.

Is this just a typo or am I mistaken about this model?
It bugs me that all the numbers come out right with 7 k?...

I've tried to ask this question on the analog devices support forum but no luck. Same with their "report error in datasheet" form.

[1] http://www.analog.com/media/en/technical-documentation/data-sheets/ADCMP606_607.pdf

* Yeah, it's clear from the datasheet that resistance is a lot higher above 1.25V, but we don't care about that. And there is ESD clamping diodes, obviously, that kick in at the edge of the supply range.

[David Hess]

You are right, the datasheet is misleading or just plain wrong.  Maybe nobody at Analog Devices knows what it means either.

Figures 8 and 9 are consistent with a 70 kilohm external resistor operating against a 1.25 volt voltage source and this conflicts with the +/-0.1 milliamp specification for input low of the latch enable function and operation with an open drain/collector driver which could leave the part latched off permanently.