Author Topic: OPA2388: peak-hold detector circuit affected by opamp input leakage current  (Read 5008 times)

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Offline brumbarchrisTopic starter

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I do not really need 1ms of hold time, as I plan to sample the peak detector output with an ADC in a 200us window after the peak. But I would obviously like the cap charge degradation in this window to be as small of possible, below 1mV, if possible.
So yeah, I will need to look at faster opamps.
I went through this article (https://www.analog.com/en/technical-articles/ltc6244-high-speed-peak-detector.html), which discusses some higher speed (200kHz max) peak detector using the LTC6244. Whereas using the "improved" topologies suggested in the article is not practical for us (due to the necessary -8.5V negative biasing voltage required, I take it from the article that the LTC6244 would be suitable at these speeds. It has a limited Vcm to 3.5V though, and I will need to detect peaks as high as 4.5V.

I have also watched this video suggested in the posts above (https://www.youtube.com/watch?v=5Pz7Mx0WRUk&feature=youtu.be&t=138), and this guy is proposing replacing the 1st opamp in the loop with an actual comparator (so this is something I will also look into, although first ever best preferred approach is to find out a suitable opamp that will work in my current schematic)

 

Offline StillTrying

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This is a good idea and I will consider implementing it.

The first one I drew is near enough what Kleinstein said on the last line of his post.

But I've just measured the rise time of my signal and it is some 6us.

From that I'm not sure a large speed increase is needed. The op amp output having to change by about 2.5 V in 6 us is only about 0.4/us, and less than 1mA charging a 1nF, even if the output has to come out of saturation 2.5V/us seems like enough, but you do have to stay long way off the data sheet's max. slew rate because there's usually quite a few things it hasn't said about what happens there such as a large loss of GBW at least!

From your last post the ADC's sample time sounds like the most important, for most digiltal ???  ADCs it doesn't matter if the input droops while it's converting because it's then using it's own sample.
.  That took much longer than I thought it would.
 

Offline brumbarchrisTopic starter

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Hi
Our ADC will sample at about 2us intervals and will take in a 200us window 3 samples that it will average.

Coming back to the peak detector: I have also found somethting else in the datasheet of the OPA2388 that might make it unsuitable, apart from the relatively low slew rate: it is the phase shift (see attached graph).
It seems that it introduces a phase shift of -90 degrees across quite a large portion of the bandwidth, including the 60kHz I am dealing with. And considering that I have two opamps, somewhat in series (the feedback of the 1stone taking the feedback from the output of the 2nd one) this can result in a rather nasty 180 phase shift. Of course, the graph is only showing the open loop phase shift, I am not sure how to relate that to my current circuit, as I have the overall circuit operating with a unity gain, more or less.

Regards,
Cristian
 

Offline Kleinstein

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The "improved" configuration in the AD article is using the diode outside the loop. So this is a 2 sided change: it makes things faster, but it also reduces the precision.
At high speed the classical version is also not perfect - because of delays and the limited BW. So it depends on the length of the pulses which version is actually better.

For the high speed range I also remember some discrete transistor based versions that may be an option.

I would not expect 1 mV accuracy to be possible. Some droop from the capacitor may be more acceptable than high capacitive loading to the OP. So I would definitely consider a smaller capacitor - more like 20-100 pF for high speed, as this can allow a faster OP.

The 90 deg. Phase shift is normal for open loop operation. The curve for the OPA2388 is actually quite good, as even at unity gain the phase shift is only 90 degrees and not more like 120 as with many other OPs.
However those phase shift plots have to be taken with a grain of salt: they can change with load current and also a capacitive load.
 

Offline brumbarchrisTopic starter

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Quote
The curve for the OPA2388 is actually quite good, as even at unity gain the phase shift is only 90 degrees

Which figure in the datasheet did you see that in? I am having trouble finding it myself.
And even if it were 90 degree, would this not give me trouble with two cascaded opamps? Is that not a sumation that I need to make (meaning 90degree from 1st opamp + 90degree from 2nd opamp = 180degree -> oscillations)?

Regards,
Cristian
« Last Edit: March 06, 2020, 03:04:15 pm by brumbarchris »
 

Offline Kleinstein

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The diagram is the one attached. The 2 nd OP is working with feedback. The feedback reduces the phase shift for much of the lower frequencies. even the about 90 deg. Phase shift near 10 MHz is still critical and chances are the circuit is still at the edge of oscillation. This is why it would really help if the buffer is faster than the 1 st. OP. One may be able to slow down the 1 st OP a little with some capacitance or RC between the inputs. I am still not sure how much this help with the nonlinear FB.

One could consider a solution with a single OP and a JFET as buffer amplifier - chances are the JFET as a source follower is quite fast compared to the usual OPs. DC errors from the FET are still compensated by the OP.
 

Offline AE7OO

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Hi,

I did not see a posted speed(or I missed it), so I'll go ahead throw my goto sample and hold into the mix.

Years ago I picked up a couple of tubes of NS LMC660's at a hamfest.  You'll have problems finding anything with a lower input bias current(2fA) or input offset current(1fA).  There is an app note floating around detailing the problems trying to measure them. It's offset voltage of 1mV is not too bad.  Common mode input range includes ground or below.

When combined with a decent CMOS switch on the input(one of the 4066's is what I use) and a PP (or one of my horded Sprauge(sp) mil-spec hermetic polystyrenes, also hamfest)  cap, and using deadbug construction makes a very low leakage S&H.

I've used it up to about 200Khz.

I just use the diagram from the datasheet.
 

Offline brumbarchrisTopic starter

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Quote
using deadbug construction makes a very low leakage S&H
Actually, I really need a peak detector, not just a S&H; unless, that is, if there is a way of determining when the maximum in the waveform occurs, in order to open the switch off the S&H at that particular moment.

Quote
One could consider a solution with a single OP and a JFET as buffer amplifier
I eventually got it to work...sort of; using an Analog Devices AD8656ARMZ, which is foot compatible to the OPA2388. So it does work, but the error is unacceptable high. So I conclued that it is probably better to go and use to different opamps, as you suggest above. As I determined it with my experience in this circuit so far, the characteristics required for these to opamps are:
- first opamp in the chain (the one charging the cap) must not necessarily be a CMOS /JFET input one, but it must have:
        - low offset voltage
        - extremely good slew rate
        - high output current
        - RRIO (my input signal range is some 0...4.5V)
- second opamp in the chain must definitely be a CMOS /  JFET input one and it must have:
        - low input bias current
        - lowest possible phase shift; this is actually critical. Every bit of phase shift will result in a delay in the feedback loop which essentially delays the first opamp to "sample" the input signal and recharge the capacitor; actually, this is a big problem I have, because I am not sure how to infer the phase shift of an opamp at Gain=1 from the information available in the datasheet. Most datasheets provide a graph with the phase shift in open loop conditions.
        - RRIO

Best regards,
Cristian

 

Offline Kleinstein

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Low phase shift in closed loop operation as a buffer kind of means high speed. So the 2 nd OP should be at least as fast as the 1st one, ideally more like > 5 times faster.
How critical the leakage current is depends on the hold time needed. So how long until the result is read. Depending on the application there can even be an advantage of there is a defined bias current (for one application I used an LF356 together with an LM318 - with the BJT intentionally as the buffer, as the bias provides a defined drift in the right direction). For a short time leakage is not that bad.
If long time analog hold is really needed one can add a second, slower stage.

The AD8656 is not such a bad choice.
 

Offline brumbarchrisTopic starter

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I am not sure why you indicate the second opamp should be faster relative to the first one. I suppose low phase shift is something generally referenced vs the input signal frequency, rise time, etc. I mean, the voltage at the input of the second opamp will have about the same change rate as the signal at the input of the first opamp, so in this case I would consider the second opamp to be as low as possible in phase shift, period. If the first opamp is faster, then even better! Not so?

Cristian
 

Offline Kleinstein

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Low phase shift in close loop comes with high bandwidth. The speed is mainly needed for stability, not because the signal actually changes so fast.

The first OP may want good driving power for a capacitive load - this does not necessarily need high current. In parts one could get around this by using a transistor as emitter follower instead of the diode. Also the memory capacitor may need to get smaller at high speed.

For high speed rail to rail operation is often a problem. So if the signal is 0 - 4.5 V, one should consider a supply that can go a little higher. With RR OPs there often is a cross over range at something like 1.5 V below the supply. In this range the OP is slowed down to correct internal errors.
 


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