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Opamp based current limiter oscillates with inductive load
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brumbarchris:
Hi all,
I managed to get to a good point, by implementing the suggestions of several of you, see the attached circuit and plot of the load current.

One thing that was repeatedly advised was to add a damping circuit on the load. As the point of this circuit is exactly to generate that negative pulse, I would have liked to keep it as "pure" as possible. However, as it seems that subsequent signal processing of this negative pulse will also need some signal conditioning, I decided to "give in" and add a 1k resistor in parallel to it.

Another suggestion was the gate to source resistance added for the main MOSFET (U2). I used to have the R2 resistor in series between the opamp output and the gate of the MOSFET, but it was doing more harm than good this way (the whole circuit was VERY sensitive to its value, and changing it from 75Ohm to 100Ohm (for example) would make a huge difference with regards to the output oscillating or not or overshooting or not. Small margin is generally not a good thing, so then following your suggestions I moved the resistor to its new position between gate and source of the MOSFET, while directly connecting the opamp output to the MOSFET gate.

I also changed the opamp, indeed the LTC1052 was an overkill and I selected the much, much cheaper (and "general purpose" labeled) AD8541.

I guess these three main changes made the difference

One thing that duak suggested I cannot do: connect the drain of M1 to VREF. The purpose of M1 is to block the U2 main MOSFET super-fast, so moving it away from its current position would defeat its purpose.

Another modification I made was to add the diode in series with the load. It is cheaper to get a higher voltage rated general purpose diode than a higher voltage rated MOSFET. This will allow me to select a much cheaper MOSFET, as well as faster, I hope. I also adjusted the VREF voltage to limit the current at 100mA, instead of 130mA. Given the inductance of the load, this will keep the negative pulse below 100V in this configuration.

Of course, I am still left with the problem of the opamp output being short circuited to VBAT (through M1) while the current source is off. The opamp output is 60mA short circuit rated, and I also do not think it is a good idea to permanently drive it in short circuit; after all, the current source will spend more time in its OFF state, rather than in ON state. So I am currently thinking about a solution to this (it was not so much of a problem when I had the R2 connected in series between the opamp output and the U2 mosfet gate, but as I changed the connection of this resistor ... this opamp output shhorting became a problem).

Best regards (and thank you for your help so far),
Cristian
duak:
Cristian, when U2 shuts off, the inductor will generate a negative voltage to try to maintain the current that is flowing through it.  In your latest circuit this voltage will be I * R7 = 100 mA * 1K0 = 100V.  If you are trying to minimize the discharge time, you must increase the value of R7.  This means you will need to find a FET with a greater BVDSS, not easy since it is PMOS.  Also, R7 takes some current from the load inductor.  If you move D1 to be in series with R7 but still have the cathode connected to the same node, it will conduct only when VOUT is negative.

You really must have a resistor between the opamp output and the gate of U2.  In the real world, many opamps will oscillate when trying to drive a capacitive load and it may not be predicted by simulation.

I think the high frequency oscillation may be caused by the combination of the inductive load, the drain to gate (Crss) and gate to source (Ciss) capacitances of FET U2.  You can try to reduce the effect of Crss by adding some capacitance across R2. Try 1000 pF to start.
brumbarchris:
Yes, I really need and want the opamp output resistance to be there. However, if I add it, the whole circuit seems to be VERY sensitive to it, even if I use low values.
I've attached two figures. The first one shows the plot of the load current with the resistor set at 10 and 20Ohm, respectively. Huge difference, and that is for a relative minor resistance interval. Not really happy with it.

The second one contains a fundamental topology change: whereas I did add in this gate resistance between the VOPAMPOUT and VGATE nodes, I connected the C2 capacitor to VGATE instead of VOPAMPOUT. I guess I am a bit uncomfortable with 3.3nF connected directly to the opamp output, given all this talk about opamps not being suitable to drive capacitive loads. This yields better results provided that I decrease also the value of R2. If I keep it high at 10k, like in the first figure, then I get the all-familiar (ugly) oscillations (despite the damping resistor across the inductor). But if I lower R2, then it seems I can vary the gate resistor up to even 300Ohm without many drawbacks (except for the ugly "blip" occurring when the current source is ON, but that is not so bothering: except for not knowing the reason for it).

A capacitor across R2 does not seem to be doing much. If anything, if it too large (>2.2nF) it brings in some ringing on the load current, when the current source is turned ON.

Also D1 in the previous post I had was a bad idea, I was under the impression it would protect the MOSFET from the big negative voltage puls which appears when the current source is turned OFF, but of course it doesn't (it would only work if the voltage pulse was positive, which it is not, obviously).

ocset:
Hi,
What about this for a solonoid driver for you......please tell if it is not to your spec, and i am sure that i , or others, will tweak it to suit...
Attached is LTspice and pdf schem
T3sl4co1l:
Huh, why are C1 (in the first circuit) and V3 referenced to ground?  (Doesn't matter in SPICE, but a real, noisy source will mind.)

Also, does it have to be a high side driver?  Either way, your flyback signal is still beyond the rails, but it can help save on level shifting or N/P transformations (and in turn, confusions like C1 and V3).

Regarding stability, exact results depend on a lot of variables: the amp's response, the transistor capacitance, even the load's inductivity (which is probably a combination of distributed capacitance and lossy inductance).  If you can't test your SPICE models against the real parts to prove them, then you're better off setting up a general enough circuit that can be compensated on the bench by changing parts values.  (To that end, about all you'd need here is a resistor in series with C2, for a pole-zero compensator.)

You may also need/want some R+C across the output transistor, either D-S or D-G.  This adds some capacitance in parallel with the transistor's own capacitance, but makes it lossy, tending to dampen oscillation.  Specifically, lossy at the crossover frequency (which is in turn set by Z_load and Coss, and opamp GBW and compensation), so the exact value of R and C depend on the loop response.  Downside: the output impedance is affected, so that it has a more resistive characteristic towards the cutoff frequency.

Ultimately, this limits the bandwidth of the signal you're looking for.  This is inevitable: you can do better or worse with various circuits, and component choice, but you can't have -- and wouldn't want -- something with infinite bandwidth.

More generally, you may consider a circuit that's not trying to be an ideal impedance, but just starts out as whatever in the first place, and your signal is measured as a ratio of voltages or currents or impedances.  An impedance bridge, for example.

Tim
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