Electronics > Projects, Designs, and Technical Stuff

Opamp based current limiter oscillates with inductive load

<< < (4/5) > >>

brumbarchris:

--- Quote ---What about this for a solonoid driver for you......
--- End quote ---

--- Quote ---Also, does it have to be a high side driver?
--- End quote ---

Well, it has to be a source, not a sink. So high side driver is needed.


--- Quote ---Huh, why are C1 (in the first circuit) and V3 referenced to ground?
--- End quote ---
What should I reference them to? Isn't ground supposed to be the most "solid" thing in the circuit?


--- Quote ---You may also need/want some R+C across the output transistor, either D-S or D-G
--- End quote ---
Do you mean a R in series with a C, or a R in parallel with a C? In fairness, I tried a C in parallel to R2, did more harm than good.

I guess the only thing I am unhappy about now is the fact that I have C2 connected at the gate of the main MOSFET; whereas I guess it is good to prevent the opamp output driving the capacitance directly, most of the schematics I've seen around have that capacitance connected at the output of the opamp.

Anyway, I am planning on ordering the components and trying a real circuit this week. Who knows, maybe it will work better than in simulation. We all know about Murphy, but my boss also has a good saying: "we must also have good luck, from time to time" (I know, not a good engineering practice to rely on that!).

Regards,
Cristian



T3sl4co1l:

--- Quote from: brumbarchris on May 06, 2019, 06:46:20 am ---
--- Quote ---What about this for a solonoid driver for you......
--- End quote ---

--- Quote ---Also, does it have to be a high side driver?
--- End quote ---

Well, it has to be a source, not a sink. So high side driver is needed.
--- End quote ---

So it's a source because it's a source?  Or is there some other reason?

It could also potentially be a negative sink, still being common ground (if that's the underlying reason).  But that would involve the same annoying level shifting so it wouldn't help any.



--- Quote ---
--- Quote ---Huh, why are C1 (in the first circuit) and V3 referenced to ground?
--- End quote ---
What should I reference them to? Isn't ground supposed to be the most "solid" thing in the circuit?
--- End quote ---

Ground is relative, as all voltages are.  The op-amp is comparing a reference voltage to a voltage drop across a resistor (which happens to be sensing output current, the intended variable).  That resistor is referenced to VBAT.  Likewise, the PMOS is referenced to its source, which is connected to VBAT, or something near it.



--- Quote ---
--- Quote ---You may also need/want some R+C across the output transistor, either D-S or D-G
--- End quote ---
Do you mean a R in series with a C, or a R in parallel with a C? In fairness, I tried a C in parallel to R2, did more harm than good.
--- End quote ---

"+" means series; "||" means parallel. :)



--- Quote ---I guess the only thing I am unhappy about now is the fact that I have C2 connected at the gate of the main MOSFET; whereas I guess it is good to prevent the opamp output driving the capacitance directly, most of the schematics I've seen around have that capacitance connected at the output of the opamp.

--- End quote ---

Yeah, don't do it that way, put an R in series with the C instead.  Works better than trying to compromise with the series resistance and FET capacitance.

This, plus a resistor in series with C:



Tim

brumbarchris:
Thanks for the reply and suggestions.


--- Quote ---So it's a source because it's a source?  Or is there some other reason?
--- End quote ---

The reason is that the signal of interest is the negative pulse generated by the inductor which appears when switching off the current through the main MOSFET. We find it much more convenient to have this referenced to ground than to VBAT, despite it being negative.

Best regards,
Cristian

ocset:
What about the attached one?...give me a shout if you want more work on the overshoot  when it turns the solonoid on.
..or maybe it helps to have a bit more current when the solonoid is turning on...to overcome inertia?

brumbarchris:
So, as advised, I referenced the + input of the opamp to VCC, (instead of ground) and I have also added the C1 and R11 circuit elements (see updated schematic). But no matter how far away I play with the values of these components (and others, like R4, C2, R2) I cannot get rid of the horrendous current blip through the load!

Not sure why this appears. If it were a phase shift problem, I would expect it to result in perpetual oscillations. As it only appears once, could it be resonance? Could it be some parasitic of the M1 mosfet (rather than the main U2 mosfet) causing it?

I've also attached the actual LTSPICE simulation, for whoever is interested in giving it a "hands on" (well, virtual, at least).

Best regards,
Cristian

Navigation

[0] Message Index

[#] Next page

[*] Previous page

There was an error while thanking
Thanking...
Go to full version
Powered by SMFPacks Advanced Attachments Uploader Mod