Folded cascode would have its bases held at constant voltage and collectors loaded with a mirror rather than a pair of equal, stiff current sources. But it's a similar thing in principle, I think.
Here those "cascode" transistors track voltage across R3 and transfer it to R4. At some high frequency, parallel capacitance across R3 kills those voltage swings to eliminate phase delay through the phase summing circuit from the amplifier's forward path, apparently.
edit
Okay, I will try more clearly. In a classic folded cascode amplifier, Q3 transfers Q1 current swings to a PNP mirror above and phase summing occurs between the output of said mirror and Q4. Here, phase summing occurs between R4 and Q4 and Q4 is just a cascode over that node, while the Q3,Q5 circuit is basically a voltage follower, with +1Vbe offset rather than -1Vbe as usual. Observe that Q3 current is fixed by QB7.