Opamps - Die pictures

[Noopy]

With a second thought about the TLC22x2 my explanation was not completely right. The output stages would probably consume more current going from the TLC2272 to the TLC2252 not less.
In addition with the difference in slewrate and noise voltage there has to be a variation of the current in the input stage. Are the differences in the output stage incorrect or additional differences beside the current in the input stage? For me that is unclear... 

[Noopy]

I have sorted my opamp section:

Small-Signal-Opamps (Bipolar/JFET/MOSFET):
https://www.richis-lab.de/Opamp.htm

Power-Opamps:
https://www.richis-lab.de/Opamp_pwr.htm

Instrumentation amplifier (more coming soon):
https://www.richis-lab.de/Opamp_instr.htm

Comparators:
https://www.richis-lab.de/Opamp_comp.htm

Voltage Follower (don´t know if there will ever come more):
https://www.richis-lab.de/Opamp_vfol.htm

[iMo]

Still no choppers? 

[Noopy]

Still no choppers? 

So much to do....
Would a LTC1051 be ok?

[iMo]

Just asking, it is not a request 
Any chopper will do, indeed, as we do not any yet, afaik..

[Noopy]

The OPA604 seen here was purchased via Ebay. The seller has already sold a three-digit number of these opamps. The slightly furrowed surface and the somewhat clumsy Burr-Brown logo arouse suspicion.




In the close-up, the lettering appears somewhat faint. A layer is coming off at the side edge. Most likely, the package was sanded down and painted before the new lettering was applied.




The OPA604 is an opamp optimized for audio applications. It has JFET inputs and, according to the datasheet, is balanced with a laser.






The dimensions of the die that can be found in this part are 0,83mm x 0,69mm. It is certainly not an OPA604. Two opamps are integrated in this circuit. At the lower edge are the input transistors, which are PNP transistors. In the upper area you can see the large output transistors.

The design strongly reminds of the fake NE5534 (https://www.richis-lab.de/Opamp11.htm). As described there, the design is similar to the Raytheon RC4558N.






There are two symbols on the die that cannot be assigned. One symbol seems to represent the characters P004. The other symbol seems similar to a snail shell. 


https://www.richis-lab.de/Opamp71.htm

 

[magic]

Chances of scoring genuine Burr-Brown chips on auction sites are low. Too much audiophool demand for them.

Same logo was found on an LM324 pretending to be TL074 on eBay and LM358 sold as OP07 on AliExpress. See here and my image a few posts below.

Regarding actual OPA604, there is further information about internals in two patents mentioned in the datasheet. This includes the output stage and "distortion rejection circuitry", which is simply a sort of "clever" driver for the P-JFET active load. The FETs are controlled by an NPN differential pair which maintains equal voltage on both sides of the folded cascode. This provides differential cancellation of base width / channel length modulation effects (to some extent), increasing open loop gain and reducing distortion.

[Noopy]

The OPA604 is an interesting device. Probably I will take some pictures of a real one.

This "logo" seems to be wide spread. Would be interesting which company that is.

[Noopy]

[...]




[...]


https://www.richis-lab.de/Opamp59.htm

Someone gave me a hint regarding this strange symbol:
These are the letters dfb which probably stand for Derek F. Bowers, a famous guy working for Precision Monolithics and Analog Devices.

 

[Noopy]

With the A109 the Halbleiterwerk Frankfurt Oder manufactured a variant of the widely used opamp µA709. The B109 was a better bin. The letter C stands for the ceramic package. The datecode AT refers to a production in January 1977.




The package consists of two ceramic elements. The mass that connects the two halves is somewhat unevenly distributed. The pins are rusting at the package.






The edge length of the die is 1,2mm. The unused area around the active area is surprisingly large. Perhaps this was to create a buffer area for the separation process. The irregular edge in the lower right corner shows that the separation process was somehow problematic.






There are a lot of cracks on the surface of the die. This appears to be damage in the passivation layer. Similar cracks were found on the MAA723 (https://www.richis-lab.de/LM723_04.htm).




A schematic of the A109 can be found in "Halbleiterinformation 117", much of the content of which is also printed in the magazine "Radio Fernsehen Elektronik" (24/1976). The circuit diagram corresponds to the circuit diagram in the datasheet of the LM709.



[...]

 

[Noopy]

For the A109, part of the mask set has survived. Only the mask of the metal layer and the mask defining the contacts between the metal layer and the active areas are missing.




Without more detailed analysis, you can already see the markings that were used to align the masks. These are two points each on the left and right edge (green/yellow), which lie on top of each other when the masks are in place. The green marked points are still visible on the present die, the yellow marked points have been cut off.

The blue marked structure allows to check the alignment of the masks against each other. These are four squares arranged within a larger square. As will be shown, for the masks that introduce an n-doping, the squares are set at the top left and bottom right, while for the p-doping, the squares are open at the bottom left and top right.

In the lower area, another auxiliary structure is shown (cyan). However, only two masks contribute to this structure.




The masks make it easier to analyze the structure of the integrated circuit. The starting material is a p-doped substrate. It is protected by a silicon oxide layer. For the sake of clarity, silicon oxide layers are not shown.




In a first process step a strong n-doping is introduced into the p-doped substrate. The n-doping later serves as a low-resistance collector feed line under the collector ("buried collector".




The mask for the buried collector matches the structures on the present A109. It can be recognized by the optically strongly protruding edges.

The high n-doping is located under each active structure except the PNP transistor T13 at the right edge. This transistor is a substrate transistor, a vertical transistor that uses the p-doped substrate as a collector. Vertical PNP transistors have better characteristics than lateral PNP transistors. But you can use them only if the collector should be connected to the negative supply potential.




After inserting the buried collector, a n-doped layer is applied using epitaxy. This layer covers the entire surface of the wafer.




At the points where isolated areas are required, p-doping is introduced into the epi-layer. The p-doping extends to the substrate and forms a well that isolates the active regions as long as the substrate has the lowest potential of the circuit.




Looking at the mask of the p-doping just described, we see that this not only creates isolated areas for the active elements. The areas under the bondpads are also isolated from the rest of the circuit. Only the bondpad in the lower right corner is an exception. The negative supply potential is transmitted via this bondpad, which is connected to the substrate.

In the active structures, the n-doping of the wells hardly stands out optically. It can be confined via the surrounding structures. In the next step, the isolation frames are widened. This means that the surroundings of the narrow isolation frames do not yet contain the n-doping. The boundary of the n-doping is the edge surrounding the buried collector. Above the buried collector, of course, there is this n-doping too.




In the next step, the p-doping is introduced, which, among other things, represents the base layer of the NPN transistors. At the same time, resistors can be represented with the base doping. As will be shown in a moment, this process step also strengthens the lateral isolation of the active areas.




The mask of the p-doping forms the base areas of the NPN transistors, collector and emitter areas of the PNP transistors and the resistors. In the NPN transistors, the base areas can be seen relatively well, since they are only overlaid by the smaller emitter area.

The mask pattern shows that the p-doping also reinforces the isolation around the active areas. This means that not only the narrow frame structures are p-doped, but also the immediate surroundings.

In the lower right corner of the die, one can see that the negative supply is connected to the isolation frame and thus to the substrate too.




Finally, a strong n-doping is introduced, which represents the emitter areas. It also forms the contact areas to the collector. A direct contact of the metal layer with the weak n-doping would form a Schottky contact, a diode. In addition, the strong n-doping in the contact area provides lower resistances in the path to the collector.




The mask of the strong n-doping has corresponding cutouts where the emitters are located and where collector areas are contacted. On the die, the collector contacts are usually hidden under the metal layer. The emitter areas are deposited by their edges in the innermost part of the transistor structures.

The NPN transistor T10 has a special shape. Together with the transistor T11 T10 serves as a current source for the differential amplifier at the input. Why this shape was advantageous remains unclear. The two transistors must have different base-emitter voltages. Probably this is the reason for the special construction.

Also noticeable are the two PNP transistors T9 and T13. Here the strong n-doping acts as a low impedance base contact. At T13, the vertical PNP transistor, the highly doped area circles around the entire active area to get a very low base impedance.

The large n+ area in the upper right area is a low impedance connection of the well to the positive supply. This is necessary because the highside transistor of the output stage is located in this well. With high currents through this transistor there is the possibility that the potential of the well shifts and the resistors integrated in the same well are influenced.




After completion of the active structures, an insulating silicon oxide layer is applied to the entire surface of the wafer. After that contacts to the active area are etched. The mask for this process are missing.




A metal layer is then applied over the entire surface of the silicon oxide layer and structured with another mask, which is missing too.

Finally, the entire wafer is covered with a passivation layer that protects the active elements from environmental influences (not shown here). This is probably silicon oxide. On more modern circuits silicon nitride is usually used. Where the bondwires are to contact the metal layer, openings must be etched into the passivation layer. This requires another mask, which is missing too.




Instead of the mask for the metal layer, the A109 document contains a kind of a wiring diagram, which shows where the individual elements are located.

Next to the resistor R11 there is a slightly shorter, unused resistor (yellow). By varying the metal position you can use this resistor as R11 or even connect both resistors in parallel. Thus it is possible to adjust the bias of the differential amplifier at the input.






With the above conclusions, one can assign all structures on the die to their functions.


https://www.richis-lab.de/Opamp72.htm

 

[Noopy]

After inserting the buried collector, a n-doped layer is applied using epitaxy. This layer covers the entire surface of the wafer.




At the points where isolated areas are required, p-doping is introduced into the epi-layer. The p-doping extends to the substrate and forms a well that isolates the active regions as long as the substrate has the lowest potential of the circuit.




Looking at the mask of the p-doping just described, we see that this not only creates isolated areas for the active elements. The areas under the bondpads are also isolated from the rest of the circuit. Only the bondpad in the lower right corner is an exception. The negative supply potential is transmitted via this bondpad, which is connected to the substrate.

In the active structures, the n-doping of the wells hardly stands out optically. It can be confined via the surrounding structures. In the next step, the isolation frames are widened. This means that the surroundings of the narrow isolation frames do not yet contain the n-doping. The boundary of the n-doping is the edge surrounding the buried collector. Above the buried collector, of course, there is this n-doping too.

There was a small mistake:
The epi layer is n-doped and the following doping is p and forms the walls of the wells.
Due to hot-linking the pictures above are no correct and the text was modified. 

[Noopy]

Here we have an A109 built in October 1980 (MO), three years later than the previous one.




Here the mass joining the two ceramic parts is somewhat irregular like we have seen it with the previous A109.






Compared to the 1977 A109, a reduction in the outer area reduced the silicon needed from 1,2mm x 1,2mm to 1,0mm x 1,0mm.




Functionally, the 1980 A109 has the same structure as the 1977 A109. The auxiliary structures for monitoring the alignment of the masks have been moved to the bondpads in the upper left and lower right corners. The small structure at the bottom edge has been dropped. A test transistor has been added to the top area of the die. To integrate this, a resistor has been relocated a little. In addition, the alternative resistor for setting the bias in the differential amplifier has been omitted. Otherwise, the structures are identical.




An irregularity can be found between the input bondpads. It is difficult to say whether this was a weakness in the manufacturing process or whether it is damage caused by an electrical overload.


https://www.richis-lab.de/Opamp73.htm

 

[edavid]

Here the mass joining the two ceramic parts is somewhat irregular like we have seen it with the previous A109.

FYI, that is called frit.

https://en.wikipedia.org/wiki/Glass_frit_bonding

[Noopy]

Here the mass joining the two ceramic parts is somewhat irregular like we have seen it with the previous A109.

FYI, that is called frit.

https://en.wikipedia.org/wiki/Glass_frit_bonding

Yeah, this strange glass stuff... 
Low temperature melting glass is somehow weird...

[Noopy]

Texas Instruments has a NE5532 in its range, which can be obtained as NE5532, NE5532A, SA5532 and SA5532A. The SA5532s are specified for an increased operating temperature range of -40°C to 85°C. For the A variants, a maximum noise voltage is specified in addition to the typical noise voltage.

The circuit diagram above is from the Texas Instruments datasheet. The functionality of the circuit is described in detail in the Philips NE5532 framework.




The areas of the two symmetrically constructed opamps can be clearly seen.




The elements of the input amplifier (green) that are sensitive to temperature gradients are arranged in such a way that they are affected as little as possible by the heat dissipated of the output transistors (red).




In the middle of the die is the designation 5532B and the year 1999. The B could stand for a second revision of the design.

A large part of the circuit is taken up by the four large capacitors.


https://www.richis-lab.de/Opamp74.htm

 

[Noopy]

The Ferranti ZN459 is a special, very low noise amplifier. The white noise at higher frequencies is typically only 800pV/√Hz and 1pA/√Hz respectively. At a frequency of 25Hz, 3nV/√Hz is specified. According to the datasheet possible applications include infrared imaging and microphone amplifiers. The cutoff frequency is typically 15MHz.




The ZN459 is not a classic differential amplifier. The datasheet contains a block diagram. It shows two amplifier stages. The feedback is integrated in the device. This is emphasized in the datasheet as particularly beneficial if one has to evaluate many channels. A center tap of the feedback resistor is connected to a pin and must be connected externally with a capacitor. A differential input is not available. Besides the signal input, the first amplifier just has a connection for the reference potential of the signal.




The datasheet also contains a somewhat more detailed block diagram showing details of the input and output stages. As could already be seen in the first block diagram, the input is not differential. It is just a simple amplifier with one transistor. To minimize noise, the emitter has to be connected to the signal reference. If you want to adjust the gain of the ZN459, you have to insert an emitter resistor. However, this increases the noise of the circuit. The feedback feeds directly into the input.

The current consumption of the ZN459 is typically 2,5mA (at 5V). 0,5mA is the current through the input stage. A not too low current in this path is important to keep the noise level low. At the input, the noise level is especially critical since it still experiences full amplification. Above the input transistor is a transistor that provides a constant collector potential (cascode circuit).

At the output, a class A amplifier stage is implemented, in which a NPN transistor operates against a 0,9mA current sink. The output has its own reference potential to keep the input free of interference.






Unfortunately, the die was damaged a little. The edge length is 0,8mm. The string 6214-III seems to be an internal project designation. In the upper corners you can see the auxiliary structures of six masks, which among other things make it possible to check the alignment of the masks against each other.




A test structure is integrated at the upper edge (pink), representing a transistor. In the lower area and on the right edge, further test structures with smaller testpads are shown (red). On the right are two resistors, most likely made of the base material. On the resistor at the bottom edge, you can see an additional square structure above the resistor strip. This is a pinch resistor, where an n-doped rectangle constricts the p-doped strip, increasing the resistance value. The circuit marked with the X contains a transistor and thus represents an emitter follower.

In the active structures, the large transistor in the left area is particularly noticeable (green). This is not the output transistor (blue), but the input transistor. In addition to the relatively high bias current in the input amplifier, this large active area ensures low noise. Extending from the output to the input are the two 180kΩ resistors, each constructed from six pinch resistors (yellow/orange). The datasheet speaks of a "matching" of the amplification factor. There is no matching to be seen here. Probably one wanted to show that the integration of the resistors is well mastered. The gain is specified with 60dB +/-1dB.

The reference potential at the input is just used for the input amplifier. In addition to the input transistor, the circuit that generates the auxiliary potential for the cascode is connected to this reference too. The reference potential of the output is distributed in a star configuration via four lines. The first line serves just as a shield for the input circuit. The second line supplies the central amplifier block. The third line serves exclusively as reference potential for the output transistor. The fourth line sets the potential around the output bondpad and appears to be used for a current source at the input. This area in the upper left corner is somewhat damaged and correspondingly difficult to read. However, you can see that there is a transistor, not a resistor, in the input amplifier supply.


https://www.richis-lab.de/Opamp75.htm

 

[Noopy]

I wasn´t right in every point of the ZN459:




The global feedback with the two 180k resistor is not a negative feedback but a positive feedback! I assume that should enlarge the input resistance that in the first place is quite low.

[Noopy]

The LH0033 is a fast voltage follower built by National Semiconductor. The maximum permissible supply voltage is 40V. The maximum allowed output current is +/-250mA. The variant with the index C is the slightly worse bin of the device. The following data applies to the better bin. The JFET input stage allows an input current of 10nA to be maintained over the full operating temperature range. The slew rate is specified by the datasheet as typically 1500V/µs. The bandwidth is specified as 100MHz.

The letters LH indicate that this is a hybrid circuit. The circuit is built on a ceramic substrate and much of it is protected by a ceramic cap. Besides this package, the LH0033 was also available in a relatively large TO-8 package.




The datasheet shows the relatively simple, two-stage circuit of the LH0033. Application Note 48 describes the circuit in more detail. In the first stage there is a JFET amplifier with a JFET current sink. Q4 generates a bias current that can be controlled with the help of R2. According to the application note, the current is 10mA. Via D1 and R2 a voltage of about 1,1V is established. A voltage of 1,1V is then also established between Gate and Source of Q1. If the characteristics of D1 and R2 are similar to the characteristics of R1 (including R3) and Q5, then the potential at the input corresponds exactly to the potential at the output. Furthermore, if both JFETs Q4 and Q5 have very similar characteristics, then the offset drift of the circuit is very small.

In the second stage, a push-pull output stage with bipolar transistors ensures that the output current does not stress the JFET amplifier stage. Transistors Q2 and Q3 set a certain quiescent current in the output stage, reducing takeover distortion.

With four supply pins, the LH0033 allows the input stage and the output stage to be supplied separately. Two additional pins allow to influence the bias current of the input stage and thus the offset voltage.






The circuit is simple. The JFETs Q1 and Q4 in the input stage are placed directly next to each other so that they have as similar temperatures as possible, which ensures a low temperature drift. D1 is relatively far away from Q2, which is not ideal. However, perfect placement of all components is difficult to achieve. Resistors R1 and R2 will have some temperature drift too and are very far apart.

To keep the quiescent current through the output stage as constant as possible, transistors Q2/Q3 have been placed in close proximity to output stage Q5/Q6.

The resistors that had to be tuned are outside the cover. Probably the tuning of the resistors was done after closing the cover.








The naming on the JFETs shows that they are Process 51 JFETs from National Semiconductor. This type is described in more detail in the National Semiconductor FET Databook from 1977. The gate can be contacted on the surface or through the substrate.






The NPN transistors Q2/Q5 show a typical structure. The metallizations on the base and emitter area allow a contacting on two sides. Both transistors have some discoloration in the emitter area and partly in the base area too.






The PNP transistors Q6/Q3 have a dirty appearance. It is also noticeable that these transistors were contacted with test needles, which could not be seen on the NPN transistors. There is a metal frame in the outer area, which appears too narrow to be contacted. It is probably a protection of the interfaces in the outer area of the transistor.




Diode D1 is another NPN transistor where the base-emitter path is used as a diode. Here, damage is clearly visible in the upper left corner. Presumably, a current flow occurred in reverse direction. Since this is a base-emitter path, the breakdown voltage must be very low. If due to a fault there is a positive potential at pin 7 a high current can flow to the negative supply potential.


https://www.richis-lab.de/Opamp76.htm

 

[Noopy]

The device you can see here is obviously from Analog Devices and was manufactured in 1984. A research for the designation AD41632 didn´t give any clues which function is hidden behind it. As will be shown, the device is the instrumentation amplifier AD624. Maybe there war a special binning or the module was specially calibrated, so that a different designation was appropriate.






Several pins are connected to the die with two bondwires. On the right, these are the supply pins. On the left, these are the contacts for setting the amplification factor. The resistance values are very small in this area, so that small changes of the resistances in the bondwires can change the behavior of the circuit. The two parallel bondwires offer lower resistance and thus also lower, absolute temperature drift.




The dimensions of the die are 4,3mm x 2,6mm.






On the die there are the numbers 624, which refer to the AD624. The circit was obviously designed in the USA.




The AD624 datasheet Revision C from 1999 contains a picture of the metal layer. The structures differ in some places from the die seen here, which apparently dates back to 1984. The earliest mentioning of the AD624 is in an advertisement in the magazine Computer Design in February 1984. The chip we have here appears to be a very early one. The metal layer from the datasheet contains the year 1991, and this image is not found in older datasheets. This suggests that the design was updated in 1991.

Apart from a few details in the circuit, the first thing you notice is that the die from the datasheet is larger. One has extended the lower edge to integrate a test structure. There are also several letters that could be initials of developers: KH, SW and GM. This is surprising. Non-functional elements often disappear during further development.




The datasheet shows a block diagram of the AD624. The instrumentation amplifier consists of the usual configuration of three opamps, with the opamps at the input doubled up. The first amplifier serves mainly as a buffer stage. The second amplifier does most of the voltage amplification.

The AD624 contains resistors that allow various gain factors to be set (1 - 1000). Integration on the die guarantees very similar temperatures, reducing the effects of temperature drift. Since the production includes an adjustment process, the amplification factors can be specified with small tolerances. In the best binning, the deviation from the set amplification is a maximum of 0,25% (G=200, G=500).

Finally, at the output there is an output driver with a feedback and a reference input, so that voltage drops on the line impedances can be compensated.

The AD624 may be operated from +/-6V to +/-18V, typically consuming 3,5mA. The index S binning allows an operating temperature range of -55°C to 125°C. The cutoff frequency is specified as 25MHz. Current noise is 60pA, voltage noise is 0,2µV from a gain of 200 (frequency ranges: 0,1-10Hz).




The datasheet shows how very many amplification factors can be set with different interconnections of the integrated resistors without the need for external resistors.




Analog Devices has published a more detailed schematic in the document "Linear Design Seminar". At first glance, this looks completely different, but it does not contradict the simpler overview in the datasheet. There are buffer stages (light green) at the inputs. The transistors on each side are doubled, which can be seen here only by the double designation. As will be shown, the transistors are cross-connected. Temperature drifts thus affect the circuit as evenly as possible and influence the signal only very little.

The input resistors and the diodes protect the transistors from too high and too low input voltages by limiting the current flow. Bipolar transistors usually provide better common mode rejection than FETs. This results in a low offset voltage of maximum 75µV. The relatively high base currents are compensated by two current sources (orange), whose currents adapt to the respective operating points. The datasheet specifies a bias current of maximum +/-15nA for the best bin.

The AD624 is based on a concept called "cross degeneration" or "pi degeneration". Each differential amplifier branch has its own current sink (I3, I4, dark green). The resistance between the two branches (cyan) defines the amplification factor. The current sources I1 and I2 (purple) ensure that the outputs of the buffer stages behave like current sources.

Between the input amplifiers are the opamps A1 and A2 (blue, red), which do the voltage amplification. A voltage source is connected to the non-inverting inputs, which is used to set the bias (pink). In parallel to the opamps the capacitors C3 and C4 are integrated, which limit the bandwidth. The outputs of the two amplifiers directly represent the differential output of this stage.

The feedback and therefore the definition of the amplification factor is done by the resistors R56 and R57 in combination with the resistance between RG1 and RG2. The interconnection ensures that the current through the resistor RG is driven by the opamps and does not load the input transistors. In fact, the potentials and currents at the transistors actually remain constant, ensuring very linear behavior.

The four 10kΩ resistors at the output amplifier (yellow) are critical elements. Their resistances have to be as equal as possible in order not to worsen the high common mode rejection of at least 115dB in the best bin (G=500).




The individual circuit blocks are easy to identify on the die. The input amplifier is on the left and the output stages are integrated on the right. The output stages have their own supply bondpads, so that the higher currents flowing there influences the remaining circuit parts as little as possible. The four input transistors are arranged in the known cross configuration (light green). The bias current compensation (orange) was integrated in the immediate vicinity.

To the right there are the two current sinks in the emitter paths and the two current sources in the collector paths of the input transistors (dark green/purple). The associated resistors provide the geometries for matching the individual current sinks and current sources, respectively. The pins Output NULL influence the current sinks. Since an offset at this point is multiplied with the amplification factor, the offset voltage at the output can be adjusted with Output NULL. The pins Input NULL adjust the current sources and are used (without amplification) to compensate the offset at the input.

At the upper left edge of the die is the resistor network, which can be used as resistor RG. Between the input transistors and the opamps a buffer stage has been integrated, which is not shown in the datasheet (white). It consists of a pair of transistors and two current sources. To the right, at the upper and lower edge, resistors R56 and R57 follow, which feed the output signal of the opamp A1 and A2 (blue/red) back into the input amplifier. Testpads allow direct adjustment of these resistors.

The opamps A1, A2 and A3 (blue/red/yellow) occupy more than half of the right area. The unmarked circuit parts seem to represent a bias reference. The voltage source defining the potential at the non-inverting inputs of the opamps A1 and A2 is also located in this area (pink). The input transistors of the three opamps are equipped with J-FETs. These are all located with their current sources in the middle of the dies Temperature drifts in the input stages of the opamps A1/A2 are relatively uncritical as long as they occur equally in both opamps. For this reason, the off-center, horizontal placement of the input transistors is not problematic. More important is the symmetrical arrangement of the two input transistor pairs. The remaining circuit parts of the opamps A1/A2 (blue/red) extend to the right edge where the output stages are integrated.

In the case of the opamp A3 (yellow) the temperature drift is more critical. Accordingly, the input transistors have been doubled and sensibly distributed. The adjustment of the input stage is done by two very large resistors, which allow a quite accurate adjustment. The output stage of this opamp is also integrated at the right edge of the die. This arrangement and the symmetry of the complete circuit guarantee low temperature drifts. Resistors R52, R53, R54 and R55, which are particularly critical for common mode rejection, have been integrated on the edges in the right-hand section. Small capacitors are connected in parallel to resistors R53 and R55 to limit the bandwidth of the output amplifier.


[...]

 

[Noopy]

On the die, a square of the resistor material is integrated, which is used to adjust the laser process. In the upper right corner there is an area engraved with a 3. Perhaps this can be used to trace the alignment process or to record the quality of the alignment.




The resistors, which can be used as RG, offer several adjustment possibilities. Thinner elements are cut completely if necessary. A thicker element has just been cut a little. The very wide element perhaps is kept for an adjustment too.




The resistors around the opamp A3 have a special shape, which is more often found with adjustable resistors.




In the "Linear Design Seminar" Analog Devices describes why the different shapes are chosen. The easiest way is to make a horizontal cut in a simple strip. If you change the direction of the cut during the adjustment, you can adjust the resistance value more precisely. However, both variants lead to high current densities in the remaining resistance area. The third variant does not have this weakness, since the cut is made in a bulge. For this variant, however, the initial resistance value must already be reasonably accurate.




The figure above is also taken from the "Linear Design Seminar" by Analog Devices. Besides the AD624 there are two slightly different variants, the AD524 and the AD625. All three devices are still in production, but are marked as NRND ("not recommended for new design"). The AD524 seems to have been the original development. It is already mentioned for the first time in 1982 in the Data Acquisition Databook of Analog Devices. The AD524 has JFETs at the inputs to protect the device from overload. In the AD624, 50Ω resistors replace these JFETs. In addition, the integrated RG resistors have been adjusted somewhat so that several different gain factors can be set. In the AD625 these resistors are missing. They have to be added externally.




The datasheet of the AD524 also contains a picture of the metal layer, but the quality is worse. It is nevertheless clear that, apart from the input protection circuitry, the present AD624 is more similar to this design than to the picture in its own datasheet. The year 1987 can be seen in the right area.




A closer look at the metal layer shown in the AD624 datasheet reveals that the input transistors are contacted differently. In the AD624 we have here, each of the four input transistors has two emitters. The illustration in the datasheet clearly shows that there is only one emitter contact. This means that during development the input transistors were changed from two emitters to one emitter. In the datasheet of the AD524, due to the more complex metal layer in the area of the input transistors, it can be assumed that transistors with two emitters were used here too. That fits with the chronological sorting.




Another difference in the metal layer can be seen in the area of the bondpads Output NULL. This is the offset adjustment that still passes through the amplification of the device. The newer metal layer in the datasheet obviously contacts two resistors directly at the bondpads. The size of the area suggests that the resistors could be aligned. The initial offset adjustment itself is already done at the corresponding current sinks. This means that it was considered necessary to additionally adjust the path for the external adjustment. Of course it is possible to react to different tolerance levels with an external adjustment, but the behavior is less predictable. With the addition of the adjustable resistors, the two resistors down the line have been shorted.




On the die, in addition to NPN and PNP transistors, there are also p-channel JFETs. However, special interest is aroused by unusual structures, which obviously consist of two elements.








These unusual elements are combinations of PNP transistors and p-channel JFETs. The structures of the PNP transistor are somewhat self-explanatory. The emitter is a p-doped circle located in an n-doped area, which is the base. An outer p-doped ring forms the collector. The base surface is contacted with a strong n-doping.

The p-doped collector ring extends to the right to the first source contact of the JFET. In fact, this p-layer extends over the complete area of the JFET and is alternately contacted as source and drain. Above this is an n-doped layer, which is the gate. Below the p-doped source-drain layer, the silicon is also n-doped.

The red appearing stripes above and below the JFET cannot be assigned immediately. The color would speak for a p-doping, which, however, would not make sense. The colors just result from the different thicknesses of the silicon oxide layers, they do not say anything about the doping by themselves. It seems most likely that we see the heavy n-doping that serves as base and gate feed line across the entire device. The different color probably results from an additional or differently shaped layer that is just in the area of the JFET. Probably that is a special thing of the process.

In common bipolar processes, n-channel JFETs are often used as simple current sources. Integrating rudimentary JFET structures is relatively easy. However, it is much more complicated to build JFETs whose quality is sufficient for high-quality analog signal processing. Consequently, it may well be that the above JFET structures were made using a special process. Apparently, the properties of the JFETs were sufficiently important to the AD624 to justify the extra effort.




The double structures are used as current sources in the AD624. Apparently, these double structures have particularly advantageous properties.


https://www.richis-lab.de/Opamp77.htm

 

[magic]

These PNP+JFET hybrids are kind of cascodes. They don't quite eliminate Miller effect because gates are connected to the input signal instead of ground, but they improve output impedance of those lateral PNPs. It looks like there is more JFETs on this chip.

The input stage is typical for monolithic instrumentation amps. Q1,I1,A1 and Q2,I2,A2 can be regarded as a pair of two-stage opamps with single transistor input stages, together realizing the usual instrumentation amp topology. The simple input stages have -0.7V offset voltage, but it's matched between opamps and cancels out differentially, and lower noise than ordinary differential pair input stages consuming same bias current and die area. They also realize current feedback, which helps maintain consistent bandwidth over a very wide range of closed loop gains.

[David Hess]

The simple input stages have -0.7V offset voltage, but it's matched between opamps and cancels out differentially, and lower noise than ordinary differential pair input stages consuming same bias current and die area. They also realize current feedback, which helps maintain consistent bandwidth over a very wide range of closed loop gains.

More details of this type of instrumentation amplifier are available in application notes for dual and quad monolithic matched transistors like the LM395 and MAT series.

[Noopy]

These PNP+JFET hybrids are kind of cascodes. They don't quite eliminate Miller effect because gates are connected to the input signal instead of ground, but they improve output impedance of those lateral PNPs. It looks like there is more JFETs on this chip.

Sounds reasonable... 
Yes, there are more JFETs. The input stages of the opamps A1 and A2 use JFETs.

The input stage [...] lower noise than ordinary differential pair input stages consuming same bias current and die area.

Why is that? Because you just have one branch and not the typical the second branch of a differential amplifier?

They also realize current feedback, which helps maintain consistent bandwidth over a very wide range of closed loop gains.

And the input stage doesn´t have to supply the RG current. 

More details of this type of instrumentation amplifier are available in application notes for dual and quad monolithic matched transistors like the LM395 and MAT series.

I will take a look! 

[magic]

The input stage [...] lower noise than ordinary differential pair input stages consuming same bias current and die area.

Why is that? Because you just have one branch and not the typical the second branch of a differential amplifier?

If the input stage is one transistor with the base being IN+ and the emitter being IN-, equivalent voltage noise is simply the voltage noise of this transistor.

If the input stage is a differential pair with emitters together and the bases being IN+ and IN-, equivalent voltage noise is the sum of the noise from both transistors. This is 3dB  higher if both transistors are identical, while power consumption and die area are doubled. If bias and dimensions are reduced 50% to match the single transistor stage, noise increases further to 6dB over single transistor.

I think main reason we don't see such input stages in normal opamps is the slightly inconvenient 0.7V offset voltage
This, and IN- also becomes low impedance, but many applications can tolerate current feedback just fine.

In early days of transistors, such input stages were used in many audio amplifiers. Saved one transistor. AC coupling or trimming pots eliminated the offset voltage.