Author Topic: Open Drain behavior  (Read 897 times)

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Offline kkessler

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Open Drain behavior
« on: May 30, 2018, 04:50:55 am »
I'm working on a project to build a temperature/humidity meter using an STM32L0 and a Waveshare 1.54 inch ePaper display. I'm running it on a 3V coin cell, and it purpose is really for me to experiment with how low I can get the energy usage to maximize the time it can run off the coin cell.

The ePaper displays uses more then 100uA in sleep mode, which is super high, considering that the display keeps its image when totally disconnected from power, so I'm gating the ground of the device through an open drain GPIO of the STM32. I'm actually playing with 2 displays; a 3 color Black, White and Red display, and a Black and White display. Using the 3 color display, I can turn off all power to the device by turning on and off the open drain output, and everything works well, even dropping the VCC of the system to 2.4V.

When I drop the voltage of the system using the 2 color display, things go awry. At 2.8 V, the VDS of the OD output is about 35mV and everything works, but dropping the supply voltage to 2.75V, and VDS jumps to 1.1V, and things stop working. If I drive a logic level mosfet (IRLML6344) with the GPIO instead of using an open drain, the VDS of the MOSFET is less than 1mV, and the whole system works well down to below 2V.

Obviously, I'm going to use the discrete transistor in my project, but I'm wondering why the open drain output is working so poorly, especially for the 2 color display. The main difference between the displays is the is the 3 color requires about twice the current as the 2 color display (~ 8 mA vs. 4 mA). Is the higher current usage somehow keeping the internal transistor of the STM32 saturated at lower VGS (because of the lower supply voltage) than the lighter current sinking of the 2 color display, or is there another reason for this behavior?

 

Offline JS

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Re: Open Drain behavior
« Reply #1 on: May 30, 2018, 05:14:44 am »
Strange indeed.

Could you tried it out in different, more controlled environment? Like different pins at different currents?

Higher current shouldn't lead to lower voltages, it should be acting as a small resistor.

JS
If I don't know how it works, I prefer not to turn it on.
 

Offline KL27x

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Re: Open Drain behavior
« Reply #2 on: May 30, 2018, 05:15:09 am »
When you drop the supply voltage of your micro, it can't switch the FET gate (The FETs in the output pins) as hard. Resistance goes up. Voltage drop across the micro pin increases. You can't sink as much current through your output pin at lower supply voltage.

Very small FETs can theoretically start to switch at under 300mV Vgs, but this would be at enormous manufacturing and testing/screening/QA cost. In reality the most sensitive FETS start switching at something closer to 1.8V. And the Rds will not reach the sweet spot until something around 4V, even if it's called "logic level."

To top it off, if your display doesn't reach high enough voltage (because of the loss in the micro pin) it might draw more power than normal for various reasons while it malfunctions.

« Last Edit: May 30, 2018, 05:18:46 am by KL27x »
 

Offline JS

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Re: Open Drain behavior
« Reply #3 on: May 30, 2018, 05:18:43 am »
When you drop the supply voltage of your micro, it can't switch the FET pins as hard. Resistance goes up. You can't sink as much current through your output pin.

Very small FETs can theoretically start to switch as under 300mV Vgs, but this would be at enormous manufacturing and testing/screening/QA cost. In reality the most sensitive FETS start switching at something closer to 1.8V. And the Rds will not reach the sweet spot until something around 4V, even if it's called "logic level."

He said it was working fine up to 2.4V with the other display, for difference in manufacturing ending with different behaviors in the output transistors I suggested testing different outputs.

JS
If I don't know how it works, I prefer not to turn it on.
 

Offline KL27x

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Re: Open Drain behavior
« Reply #4 on: May 30, 2018, 05:21:42 am »
Different display, different current draw?
Quote
the 3 color requires about twice the current as the 2 color display (~ 8 mA vs. 4 mA

Works fine when using an external FET.

I think the mystery not so mysterious.  :-//

OP, if you wanted to push the limits in reducing parts count, you could try again with more decoupling caps on the micro supply pins. 8mA (average) draw isn't all that much, but the peak is ...?  Peak draw is probably causing dips in your power rail (leads of your adjustable power supply or coin cell).
« Last Edit: May 30, 2018, 05:28:12 am by KL27x »
 

Offline Siwastaja

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Re: Open Drain behavior
« Reply #5 on: May 30, 2018, 07:50:38 am »
Most likely the another display just draws significantly higher peak current at low voltage. It's not uncommon that some ICs may draw excessive currents at lower-than-specified voltage; this is important when ramping up voltages, you need a stronger current source than you'd expect from the normal operating current to get over the high consumption area. With your open drain pin with around 50 ohm of resistance (considering lower operating voltage and internal temperature rise within the MCU io cell), this may get your chip "stuck" at low voltage, high consumption area.

Just a guess.

Also make sure there isn't latchup happening due to input pins having illegal voltages. Switching the ground can be iffy.
 

Online David Hess

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Re: Open Drain behavior
« Reply #6 on: May 30, 2018, 08:25:36 am »
Either the current drawn by the display circuits is increasing at lower supply voltages or the lower enhancement to the open drain output transistor is not allowing it to saturate.

Some circuits and ICs will draw more current below some minimum voltage until an even lower voltage.

You could use multiple open drain outputs in parallel.

Switching ground or power can cause problems if any other I/O pins are being held low or high.
 

Offline kkessler

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Re: Open Drain behavior
« Reply #7 on: June 01, 2018, 04:30:52 am »
I did some further testing, and the TLDR; version is, using an open drain GPIO to switch the ground to turn on and off a device is a bad idea because the Rds(on) is too high.




The first scope screen shot shows the Vds of the open drain FET in yellow, and the green represents the current for the 3 color display running at 3 V. Unfortunately, my uCurrent seems to be on the fritz, because anything other 1mV/1mA range gives me way too low readings. I know the first spike is about 39mA because I had done some analysis on it earlier to figure out how much energy a screen update was using (I documented that here: https://hackaday.io/project/134018-coin-cell-powered-temperaturehumidity-display/log/145333-improved-current-measurements ). Basically I was putting resistors in parallel across the uCurrent terminals to change the ranges to get a 1mV/10uA and 1mV/100uA range, to get the voltage level out of the noise so I could see it on the scope.

I wonder if that is a bad thing to do, because, even though I did this a couple of weeks ago, yesterday my uCurrent's lower ranges stopped working. Knowing that the first spike is 39mA, the 725 mV spike says that my 1mV/1uA range is now 18mV/mA. I have no idea if it is at all linear, but I don't think that is particularly important in this analysis. You can't really see it in the screen shot because the green trace is on top of the yellow, but Vds at the spike is about 1.5V, making the Rds(on) something around 38Ohms.



The second screen shot shows the 2 color display running at 3 V. Other than showing that a screen update on the 2 color display takes less than 5 seconds while the update on the 3 Color display takes more than 10, it also shows that during the time the displays are actually shuffling the particles around inside the display, the 2 color display is using current more consistently at a higher level than the real spiky 3 color display.



The third screen shot show the 3 Color display running at 2.4 V. Here you can see why the 3 color display continues to function at the lower voltages (I tested it down to 2V successfully). At the lower voltage, the peak currents are lower, but they are drawn for a longer time, so the Vds never gets out of hand.



The fourth screen show shows the 2 Color display running at 2.4V, and  at the point where it starts to activate the display, it draws enough current to cause the Vds to reach a point where the controller on the display just kind of locks up.

If anyone disagrees with my assessment, please educate me. Thanks

« Last Edit: June 01, 2018, 04:34:48 am by kkessler »
 

Offline jbb

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Re: Open Drain behavior
« Reply #8 on: June 01, 2018, 09:33:42 am »
Late to the party... I agreed that 100uA sleep for an e paper display is weird and disappointing.

Now that you’ve identified the problem, let the power switching begin!  A P-Ch FET in line with the display Vcc should do the trick. However, switching parts of the circuit off can be tricky. I’ve made some mistakes...

Remember to check all your GPIO code to make sure the micro pins are in good states. The usual suspects are: leaving a line as output high, leaving a weak pull-up enabled, leaving a pin configured for special mode (e.g. SPI config may make a GPIO into an output high when you’re not looking).
 


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