OPENSOURCE HW/SW Grid Solar Microinverter 450W - 97% Efficiency, 25yrs Lifespan

[KoRba88]

I'm not syncing anything with the grid. There is no grid at all here, I just connected waveform generator instead of grid (original ST design also have a DAC for grid simulation tests).

The reference for the current is the reactive power calculated by multiplying direct and quadrature voltages and currents (direct and quadrature current are swapped here). By reactive power control the phase angle between current and voltage should change.

And there are used to calculate signal that goes to reverse park transform to generate PWM

Code: [Select]

    Quadrature_Current_PID.Reference = (PID_Bus_Voltage(&BUS_Voltage_PID,Bus_Voltage));

    Direct_Current_PID.Reference = (PID_Reactive_Power(&Reactive_Power_PID, Actual_QD_Power.Q_Reactive));

    Output_qId_Inverter = (s16)(PID_DirectCurrent(&Direct_Current_PID, ((Inverter_q_d.qI_Direct))));

    Output_qIq_Inverter = ((s16)(PID_QuadratureCurrent(&Quadrature_Current_PID, ((Inverter_q_d.qI_Quadrature)))));

    CrossDecoupling_Control();

    RevPark_Circle_Limitation();

    Control_Volt_AlphaBeta= Rev_Park(Output_qIq_Inverter,Output_qId_Inverter);

Seems overly complicated, in my senior design project I just divided down the mains voltage with a resistor divider, put that through a digital potentiometer to allow the microcontroller to adjust the gain, and then sent it to a common UC3843 which controls the PWM MOSFET. So basically a current output class D amplifier with the input connected to the output.

I'm now thinking that it probably would make more sense to take advantage of economies of scale and design the inverter to accept input from two panels (separate MPPT inputs) so that each inverter sits in the middle of two panels. Could possibly extend it even further to 3 or 4 panels but that would reduce compatibility with possible panel layouts.

Actually is mandatory by grid standards. In grid inverters you have to have a reactive power control also to increase active power production.
https://www.google.com/url?sa=t&source=web&rct=j&url=https://researchportal.hw.ac.uk/files/44448200/document_1_.pdf&ved=2ahUKEwi4mpL7-Nb3AhWGyosKHSB0ACwQFnoECDgQAQ&usg=AOvVaw2KKxt4owTThvi6KyTILSvZ

[moffy]

Chokes are made of soft saturating sendust with about 3A capability. Currently I'm testing it with max 0.5A (even that glitch don't have 1A)

What I mean is what happens when you blow your output devices when connected to mains? What are your fault currents then, I would guess more than 3A.

[KoRba88]

Chokes are made of soft saturating sendust with about 3A capability. Currently I'm testing it with max 0.5A (even that glitch don't have 1A)

What I mean is what happens when you blow your output devices when connected to mains? What are your fault currents then, I would guess more than 3A.

Yes, probably more but this will not solve the root cause of that zero-cross glitches, and they appear all the time, no matter if there is a no load or 40W light bulb or 200W . I have to eliminate them before connecting the inverter to the real grid.

Today I've checked all Vgs and Vds, and they look ok. Of course at zero cross Vds of LF mosfets are distorted (no matter of amount of dead time I set).

[NiHaoMike]

Actually is mandatory by grid standards. In grid inverters you have to have a reactive power control also to increase active power production.
https://www.google.com/url?sa=t&source=web&rct=j&url=https://researchportal.hw.ac.uk/files/44448200/document_1_.pdf&ved=2ahUKEwi4mpL7-Nb3AhWGyosKHSB0ACwQFnoECDgQAQ&usg=AOvVaw2KKxt4owTThvi6KyTILSvZ

You can do that by creating a delayed (by 1/4 of a cycle) version of the voltage signal and add or subtract it from the nondelayed signal.

[KoRba88]

Actually is mandatory by grid standards. In grid inverters you have to have a reactive power control also to increase active power production.
https://www.google.com/url?sa=t&source=web&rct=j&url=https://researchportal.hw.ac.uk/files/44448200/document_1_.pdf&ved=2ahUKEwi4mpL7-Nb3AhWGyosKHSB0ACwQFnoECDgQAQ&usg=AOvVaw2KKxt4owTThvi6KyTILSvZ

You can do that by creating a delayed (by 1/4 of a cycle) version of the voltage signal and add or subtract it from the nondelayed signal.

That would be very noisy and unstable.

Now I'm creating orthogonal signal of the voltage which is delayed by 1/4 (90deg) but that together with normal voltage is routed to Park transformation and to PI regulator, then to integrator PLL to create angle theta and frequency for grid synchronization. But probably the part responsible for Q control don't work properly because reactive power don't change phase angle at my command.

[jbb]

Late to the party on the zero crossing bump… the use of a slow leg (Si devices) and fast leg (SiC devices) does mean you get quite a big bump when the slow leg switches.

This is effectively a large common mode signal, and it will couple through stray capacitances to ground. If you’re using a big DC bench supply for the DC link you might have a big stray capacitance inside which is subjected to a 400V swing when the slow leg fires.

Sorry I don’t have time to dig in properly, you may already know this, but the switching of the slow Si leg is determined not by zero crossing of the AC line voltage but instead by the zero crossing of the PWM reference signal. These likely have a bit of a phase offset.

On component destruction: I recommend adding some overcurrent and over voltage trips (gate all FETs off and open relay) to your test software. That way an unstable loop will cause a trip rather than a boom. In a past prototype I even deployed analog comparators and logic chips so it would trip even if the software was bolloxed.

In that previous project, I found that you can get quite a good idea of the current control behaviour by shorting the ‘AC line’ terminals and setting the software to generate its own 50Hz reference.

[uer166]

That's a very good point about the extreme common mode swings. I've designed an experimental boost inverter and decided to use the equivalent of 2 HF half-bridges, each with their own inductor. That makes for essentially a split phase output without any high frequency CM voltages, and it plays nice with anything.

IMO swinging the CM output that fast and at that high of a voltage is never a good idea unless you have taken extreme isolation measures and keep the capacitance low between primary and secondary.

Maybe in next rev you can adapt it to output 2 phases instead of one, and remove the low frequency leg entirely..

[KoRba88]

Late to the party on the zero crossing bump… the use of a slow leg (Si devices) and fast leg (SiC devices) does mean you get quite a big bump when the slow leg switches.

This is effectively a large common mode signal, and it will couple through stray capacitances to ground. If you’re using a big DC bench supply for the DC link you might have a big stray capacitance inside which is subjected to a 400V swing when the slow leg fires.

Sorry I don’t have time to dig in properly, you may already know this, but the switching of the slow Si leg is determined not by zero crossing of the AC line voltage but instead by the zero crossing of the PWM reference signal. These likely have a bit of a phase offset.

On component destruction: I recommend adding some overcurrent and over voltage trips (gate all FETs off and open relay) to your test software. That way an unstable loop will cause a trip rather than a boom. In a past prototype I even deployed analog comparators and logic chips so it would trip even if the software was bolloxed.

In that previous project, I found that you can get quite a good idea of the current control behaviour by shorting the ‘AC line’ terminals and setting the software to generate its own 50Hz reference.

DC link is supplied internally by transformer isolated LLC stage of microinverter. That transformer have some stray capacitance since its winding are interleaved however I've added Y Cap connecting both grounds to shunt HF current noise.

Currently all MOSFETs are Si. There is no spurious turn on from miller and dv/dt product at slow and fast leg.

For protection there are low side comparators for each leg (and they works fast, 300ns from detection to shut off)

For inline current sensing there is a comparator just after the first opamp at inductor shunt. However here I have a large noise from LLC converter at 2x switching frequency (140kHz x2) so I have added more filtering to that and its not as fast. However its shouldn't be a problem since 1mH grid inductor are slowing down the current so it should works that way.

Regarding phase offset, there will be always some but shouldn't be no more than 2x of switching frequency, so max 40 us, not 500-800 us. That is definitely comes from LC filter.

[KoRba88]

That's a very good point about the extreme common mode swings. I've designed an experimental boost inverter and decided to use the equivalent of 2 HF half-bridges, each with their own inductor. That makes for essentially a split phase output without any high frequency CM voltages, and it plays nice with anything.

IMO swinging the CM output that fast and at that high of a voltage is never a good idea unless you have taken extreme isolation measures and keep the capacitance low between primary and secondary.

Maybe in next rev you can adapt it to output 2 phases instead of one, and remove the low frequency leg entirely..

Bipolar modulation require 2 inductors (equal) but is bad for THD and require higher switching frequency so loses will be bigger.

Actually that LF 50Hz reduces CM significantly since is low frequency and that Si mosfets have about 50nS turn on and 30ns turn off so its max 13V/ns, not to high.  SiC MOSFETs have a less than 10ns turn off and when I've tested them they worked fine without any CM noise problems or miller gate turn on. To reduce voltage swing only way is go to the Three Level (or more) topology inverter.

See https://ieeexplore.ieee.org/document/7930777

The authors of that paper also say something about zero-cross distortions
 
"Also at the zero crossing of the output voltage there will be some distortion in the hybrid modulation due to the discontinuous change in the modulation state (when output voltage changes from positive to negative) compared with unipolar or bipolar modulation which is continuous and do not have zero crossing problems."

However distortion =/= huge glitch. Actually after some PI tuning I've almost zero oscillations at one side of sine, and some at the other side. But glitches are still present.

[uer166]

Bipolar modulation require 2 inductors (equal) but is bad for THD and require higher switching frequency so loses will be bigger.

I admit I read your paper but I don't fully understand why the THD would be tied to which topology. The PID/DQ/2p2z/whatever control scheme is probably the biggest factor for THD. It's more or less what I tried here: https://www.eevblog.com/forum/projects/experimental-48v-gt120vac-60hz-inverter/msg3401984/. You basically have 2 independent sync buck converters, that would have same THD/noise contribution as the one you have already. Yes, you will have slightly higher losses, but IMO it's worth the transient/short protection (all silicon is behind your big inductors), and good control of CM noise. I've had serious issues once of that kind of CM coupling into control circuitry and faulting out the converter.

One issue might be that the LF HB output is swinging with really hard edges at 60Hz, which will couple through your Y-cap across the transformer into your input (e.g. if the input has same reference/ground as your output in your test).. Maybe try removing that Y-cap and instead let your transformer handle the output CM swing?

[NiHaoMike]

That would be very noisy and unstable.

Why? You're just putting the samples through a FIFO buffer so that it ends up delayed by 1/4 of a mains cycle. It only has as much noise as the input, which is easy to reduce to very low levels given you're starting with 120V or 240V.

[Phoenix]

I'm not syncing anything with the grid.

Now I'm creating orthogonal signal of the voltage which is delayed by 1/4 (90deg) but that together with normal voltage is routed to Park transformation and to PI regulator, then to integrator PLL to create angle theta and frequency for grid synchronization. But probably the part responsible for Q control don't work properly because reactive power don't change phase angle at my command.

What are you connecting the AC terminals to? A resistive load? Looks like a light bulb.

You will only be able to control the current phase angle relative to the voltage if you're connected to a stiff voltage source. Otherwise your current angle will be determined by the RLC's of the load - adding a reactive command will shift the phase relative to your internal phasor but externally the observed voltage-current phase will always remain the same.

[Phoenix]

Actually after some PI tuning I've almost zero oscillations at one side of sine, and some at the other side. But glitches are still present.

From your earlier oscillograms it looks like the minimum effective pulse width is asymmetrical for short turn on and turn off pulses around the polarity switch. Perhaps you're getting more glitch in the "small on pulse" region because it requires more duty cycle to get an effective gate pulse.

Someone earlier mentioned putting in some blanking time - ideally you need both phase legs to switch polarity at exactly the same time which it seems you have achieved pretty well.

This issue may have a different distortion characteristic when you're running reactive current because the voltage zero crossing will not longer be the current zero crossing. This may also be what is happening because the inverter is supplying the reactive current for the filter capacitors.

[Phoenix]

That would be very noisy and unstable.

Why? You're just putting the samples through a FIFO buffer so that it ends up delayed by 1/4 of a mains cycle. It only has as much noise as the input, which is easy to reduce to very low levels given you're starting with 120V or 240V.

A well designed PLL will remove grid voltage distortion from the current reference signal. Once you have the synchronous value of phase you can simply use sine and cosine to generate the direct and quadrature current components. You can also correct for any inherent phase offset in your algorithm (or sense network) by adding or subtracting a little from theta.

[KoRba88]

That would be very noisy and unstable.

Why? You're just putting the samples through a FIFO buffer so that it ends up delayed by 1/4 of a mains cycle. It only has as much noise as the input, which is easy to reduce to very low levels given you're starting with 120V or 240V.

A well designed PLL will remove grid voltage distortion from the current reference signal. Once you have the synchronous value of phase you can simply use sine and cosine to generate the direct and quadrature current components. You can also correct for any inherent phase offset in your algorithm (or sense network) by adding or subtracting a little from theta.

Good point Phoenix. Moreover GRID itself is noisy and unstable so you have to have some filtering and fast reaction time. This is not trivial task since filtering and fast reaction time are a contradictions in general meaning. Park transformations and PI acts together as a fast filter so disturbances form a grid can be reduced to some degree.

[KoRba88]

Actually after some PI tuning I've almost zero oscillations at one side of sine, and some at the other side. But glitches are still present.

From your earlier oscillograms it looks like the minimum effective pulse width is asymmetrical for short turn on and turn off pulses around the polarity switch. Perhaps you're getting more glitch in the "small on pulse" region because it requires more duty cycle to get an effective gate pulse.

Yeah but that can be due to a little offset in measured current that is feed to PI regulator. Its about 0.01% of the signal amplitude but It could have an impact.

[KoRba88]

I'm not syncing anything with the grid.

Now I'm creating orthogonal signal of the voltage which is delayed by 1/4 (90deg) but that together with normal voltage is routed to Park transformation and to PI regulator, then to integrator PLL to create angle theta and frequency for grid synchronization. But probably the part responsible for Q control don't work properly because reactive power don't change phase angle at my command.

What are you connecting the AC terminals to? A resistive load? Looks like a light bulb.

You will only be able to control the current phase angle relative to the voltage if you're connected to a stiff voltage source. Otherwise your current angle will be determined by the RLC's of the load - adding a reactive command will shift the phase relative to your internal phasor but externally the observed voltage-current phase will always remain the same.

Yeah, resistive load. I'll try with RL load (i.e bulb and 1mH toroid) to tune PI controller.

Now the plan is connect inverter to the grid with fast 1A fuses on both zero and live wire. Then start with switching off, just measure. Then LF leg only, then try the whole thing with HF PWM.

[NiHaoMike]

Good point Phoenix. Moreover GRID itself is noisy and unstable so you have to have some filtering and fast reaction time. This is not trivial task since filtering and fast reaction time are a contradictions in general meaning. Park transformations and PI acts together as a fast filter so disturbances form a grid can be reduced to some degree.

Wouldn't making it somewhat unstable help with anti islanding? Or are you intending for it to connect to an ATS to be able to switch to off grid operation and therefore need it to be able to operate in a stable manner?

[Siwastaja]

Let's be straight:

Cycle-by-cycle current limit is the first thing you do. Unless your target is some $0.01 chinesium gadget where you can't afford the sense bandwidth.

Everything else is secondary to that.

It might be that at some point, this cycle-by-cycle limit never triggers, but it is the feature which prevents inductors from saturating and semiconductor switches from blowing up, for whatever reason.

You really can't rely on your control loop and PWM control always functioning in such way that inductor saturation just does not happen. Real world is full of edge cases. Having an unexpected transient as a result is OK; blowing up the power devices is not. Because MOSFETs blow up in microseconds, you need active protection that can react within those microseconds. In other words: too much current -> turn it off quickly.

Once you have this, prototyping and developing the control loops becomes actually possible, as any mistake here can't blow up anything.

[KoRba88]

Let's be straight:

Cycle-by-cycle current limit is the first thing you do. Unless your target is some $0.01 chinesium gadget where you can't afford the sense bandwidth.

Everything else is secondary to that.

It might be that at some point, this cycle-by-cycle limit never triggers, but it is the feature which prevents inductors from saturating and semiconductor switches from blowing up, for whatever reason.

You really can't rely on your control loop and PWM control always functioning in such way that inductor saturation just does not happen. Real world is full of edge cases. Having an unexpected transient as a result is OK; blowing up the power devices is not. Because MOSFETs blow up in microseconds, you need active protection that can react within those microseconds. In other words: too much current -> turn it off quickly.

Once you have this, prototyping and developing the control loops becomes actually possible, as any mistake here can't blow up anything.

Did you read my previous posts?I have even more advanced protection called two level MOSFETs turn off circuit with shut down MOSFETs completely within 1us. It's verified but at first time when I tried to connect inverter to the grid I had to increase filtering here (and therefore reaction time) and due to some false triggering due to noise at HVDC bus with was triggering OC at inductor comparator. I have to put inductor to create LC filter on HVDC bus to filter out that noise and then the protection will work as designed.

[jonpaul]

anti-islanding is required by most electrical codes.

A permit, utility firm connection and approval as well.

A liscenced électricien required to connect

DIY installation will not be compliant, void the properties insurance and may be dangerous.

I would seek advice of local firms, also the electrician forums and Mike Holt forums of electrical inspectors.

Be safe,

bon courage

Jon

[uer166]

Did you read my previous posts?I have even more advanced protection called two level MOSFETs turn off circuit with shut down MOSFETs completely within 1us. It's verified but at first time when I tried to connect inverter to the grid I had to increase filtering here (and therefore reaction time) and due to some false triggering

If that system worked properly then you wouldn't have blown the FETs as soon as the grid got connected. Are you 100% sure the triggering was indeed false and not a real over-current event? I've had cases where I thought I had false trips, and then tried to relax/disable the OC protection, and it promptly blew up some gate drives due to it being a real overcurrent event.

I'd do some minimal single and double pulse tests in known conditions to test the overcurrent protection, before even messing with the control loop. Just create a 1 or 2-pulse train into the gate driver to generate a ramp and peak current that should trip the OC, and see if it does.

Post the inductor current in those pulse tests, would be interesting to see.

[NiHaoMike]

anti-islanding is required by most electrical codes.

A permit, utility firm connection and approval as well.

A liscenced électricien required to connect

DIY installation will not be compliant, void the properties insurance and may be dangerous.

I would seek advice of local firms, also the electrician forums and Mike Holt forums of electrical inspectors.

A workaround would be to make an "educational" version that connects via a low voltage transformer, the main intent would be to make it safer to tinker with. If you could find a ready made box that has the transformer connected to an AC cord and exposes the low voltage secondary on a connector (sadly getting harder and harder to find when switching supplies have largely replaced them), the user won't even have to do anything with the mains other than plugging the transformer in.

[KoRba88]

Did you read my previous posts?I have even more advanced protection called two level MOSFETs turn off circuit with shut down MOSFETs completely within 1us. It's verified but at first time when I tried to connect inverter to the grid I had to increase filtering here (and therefore reaction time) and due to some false triggering

If that system worked properly then you wouldn't have blown the FETs as soon as the grid got connected. Are you 100% sure the triggering was indeed false and not a real over-current event? I've had cases where I thought I had false trips, and then tried to relax/disable the OC protection, and it promptly blew up some gate drives due to it being a real overcurrent event.

I'd do some minimal single and double pulse tests in known conditions to test the overcurrent protection, before even messing with the control loop. Just create a 1 or 2-pulse train into the gate driver to generate a ramp and peak current that should trip the OC, and see if it does.

Post the inductor current in those pulse tests, would be interesting to see.

Yep, it was false triggering since it occurred as soon as I turned on LLC stage without even turning on switching at DCAC stage so without any load on inverter inductor. I have independent power supplies here so I can turn on supply for inductor current sensing without turning ON the LLC stage. Moreover OC pulses have a double switching frequency (positive and negative polarity from voltage doubler) of LLC stage.

[KoRba88]

anti-islanding is required by most electrical codes.

A permit, utility firm connection and approval as well.

A liscenced électricien required to connect

DIY installation will not be compliant, void the properties insurance and may be dangerous.

I would seek advice of local firms, also the electrician forums and Mike Holt forums of electrical inspectors.

Be safe,

bon courage

Jon

anti-islanding is implemented, simple as a thresholds of frequency and voltage driven by local grid requirements

Moreover the plan is to make commercial version of that microinverter and make a certification.