OPENSOURCE HW/SW Grid Solar Microinverter 450W - 97% Efficiency, 25yrs Lifespan

[KoRba88]

This is the project that I want to share with you. Project goal is 97% peak efficiency and over 25yrs lifespan.
I've been working on this project over two years total. Currently the project is at the software development design stage and I hope to get some support from you regarding that.
I know that Dave Jones like solar stuff so maybe this topic will get some attention.


Photo of V1 (but V2 looks almost identically)



V2 that is powering the lightbulbs

INTRODUCTION

Microinverter is based on AN4070 250W Grid connected micro-inverter by Rosario Attanasio.

https://www.st.com/resource/en/application_note/an4070-250-w-grid-connected-microinverter-stmicroelectronics.pdf

The design is based on two power stages, namely, an Resonant LLC DC-DC
converter and modified unipolar modulation DC-AC converter. Max power is 450W to align with the biggest PV modules available on the market today. Original AN4070 use interleaved boost with isolation transformer in DC-DC stage. To improve efficiency I've decided to design a resonant LLC converter which so far have 97.5% peak efficiency without any optimization. DC-AC stage is basically the same but high frequency transistors were replaced by SiC MOSFETS to increase switching frequency from original 17.4kHz to approx 50kHz. This stage have approx 98% peak efficiency, so currently total efficiency is about 95.5% (at 70% of load) with room for improvement. MCU has been changed from STM32F103 to the newest STM32G474 that is dedicated to the digital power supply control systems. Design also have a lot of other improvements (i.e voltage, current sensing, gate drive, protection) which optimize it in terms of cost and performance. To achieve a 25yrs lifespan there are no electrolytic caps here. Bulk caps are film polypropylene caps.

It contains all hardware and software required to connect the microinverter to the grid. Currently software is under development due to some control issues which I want to mostly focus on here. Microinverter AC sine voltage generationworks. It works on closed loop with PLL and Park Transformations when DAC serves as an grid signal simulator. (DAC attached to GRID side voltage amplifier). It fails however after synchronization to real GRID with massive overcurrent events and oscillations. Voltage in my grid is also non ideal, and looks like trapezoid not sine wave but that could be related to zero-cross over distortions which I'm facing now. Frankly speaking at zero cross events there are distortions of sine current that are related to modulation of MOSFETS. It happens in open and closed loop mode. Now I'm try to eliminate them.

HARDWARE

Currently hardware is a revision V2 which means it’a second prototype with significant hardware improvement (noise, signal integrity, sensing philosophy, cost optimized) over version V1.

There are two main PCBs namely DCDC stage and DCAC stage, plus couple of small PCBs with digital isolators and planar transformers that connects DCDC and DCAC PCBs.

Schematics, PCBs and GERBER files are available via github. The project structure is as follows.

DCDC.PrjPcb - Project of DCDC PCB That contains main STM32G4 microcontroller. Processor here do all main tasks. Its control LLC resonant converter with MPPT stage and DCAC stage with PLL and Park transformations. That board connects with DCAC stage via digital isolators and control planar transformer half-bridge converter to power the DCAC stage circuits. On this PCB there is also CAN bus transceiver and ESP8266 WiFi. Power is delivered by two step down DCDC. One from PV to 12V and one from 12V to 5V. There are also two 5V-3.3V LDO for digital and analog circuits.

Power_Stage.SchDoc - Contains Full Bridge LLC Mosfet stage with resonant current sensor (Resonant current sensing for future use). Here we have also connections for LLC Transformer, resonant Inductor and Capacitors. Currently the transformer and inductor are separate things. I spoke with a transformer expert here in Poland and he said that performance will be identical with integrated one but EMI will be better (yeah that horrible fringe fields form the gapped transformer). Transformer+Inductor cost under $10, but due to ETD39 size and I wanted a low profile (PCBs are designed for very nice aluminium IP67 GAINTA HQ017S enclosure) so the transformer is turned sideways so now its naturally connect both DCDC and DCAC PCBs and it fits to that enclosure. LLC stage boost 36-42V from PV (optimized for longi lr4-72hph-450m) to 200V and after that there is a diode-cap voltage doubler that makes 400V.

MCU.SchDoc - STM32G474Q with PV Voltage and PV Current sense circuits. There are also NTC, LEDs, and external VREF.

ISO_IO.SchDoc - Connectors to DCAC stage

ISO_Power.SchDoc -  is a half bridge driver for the Planar Transformer that gives power for DCAC axillary circuits.

HV_BUCK_V2.SchDoc - Is a buck connected with a PV Panel that delivers 12V. 75V max input voltage capable.

LV_Buck.SchDoc. Buck converter that is stepping-down 12V to 5V plus two 3.3V LDO, one for digital and one for analog part.

CAN.SchDoc - Isolated CANBus Transceiver with LDO supply for stepping down power supply from isolated side.

WIFI.SchDoc - ESP8266 that is connected to the STM32G474Q. Also contains a circuit with a backup supercap to be able to do some statistics at night (i.e temperature logging).

DCAC_V2b.PrjPcb - That PCB contains of course DCAC inverter bridge. Its converts 380-400VDC to the grid AC Voltage. That stage uses hybrid unipolar modulation. One of the half bridge that is connected to inductor operates at high frequency, and second leg operates at low frequency. Its reduces EMI and it optimize the cost since only one leg have to work at high frequency (SiC MOSFETS), second leg could use cheaper slow Si MOSFETs.

PCB Contains 2 microcontrollers that one STM32G431 is located at DC- ground potential and its used for HVDC Bus sensing, low side MOSFET TWO-LEVEL OFF protection, control high side MOSFET charge pumps (will be removed in next revision due to noise and replaced by second two output planar transfomer). control 21V step up converter and -3.5V for gate drivers.
Second STM32G491 is located at grid side after inductor to sense inductor current, grid voltage and HVDC Bus. I wanted to test if HVDCBus sensing here will be reliable. After testing its looks that it is so I the next PCB revision the HVDC sensing will be removed from low side MCU. So the low side MCU could be replaced to some cheaper STM only for protection and power control.

Control_Sense_BOTT.SchDoc - STM32G431 MCU with HVDC Bus and experimental High Side current measurements. Currently both signals are not used since Grid Side MCU measures HVDCBus very well and I don't have to manage two SPIs to transfer all measurements. MCU is connected to DCDC STM32G474 via digital isolators with SPI plus other signals (i.e MOSFET protection trigger from TWO-Level Protection circuit).  Also via digital-isolator mosfet gate signals are coming from DCDC stage. Two level protection uses a TIMER that after detecting an overcurrent in mosfets it cuts its gate voltage to approx 9V for SiC and 5V for Si MOSFETS for 1uS. MOSFETs here works in linear region to dissipate inductive energy (from PCB and MOSFET Leads) . That prevents high voltage overshoot that could destroy mosfets if they were to be turned off immediately. After 1uS MOSFETs gates are turned off to 0V.


IND_CURRENT_SENSE.SchDoc - Here we have all grid realted measurements. Most of them are converted to differential signals to get better precision. ADR3425 used for high long term accuracy. (Microinverter should work over 25yrs without maintanence so its not overdesign)

Inductor shunt current sense with uses one fixed 15x gain plus PGA inside STM32G491. Aim was to boost gain at lower currents to boost accuracy at low sun light conditions.
Grid Voltage sense uses simple circuit, not fancy things here.
Hall Current sensor in return path. Mainly purpose for differential current sensing tocreate a RCD like protection. Currently not implemented in software.

DRV_TOP_MOS.SchDoc - gate drivers with to level protection (there protection is controled via DCDC STM32G474). Plus overvoltage comparators.

DCAC_V2.SchDoc - Full Bridge MOSFETS, LCL filter. Inductors are made with high performance Sendust toroidal cores. They are both 1 mH with at 50kHz and 2A output current produces 20% of ripple. CMC is 10 mH. There are also two optocoupler circuits to detect open fuse at GRID and HVDC side.Grid protection is made of diff mode hybrid GDT+MOV and for common mode is two MOV+ discrete GDT.  According to solar inverter reliability studies grid protection is one of the most important things for long live inverter reliability. Here we have also relay plus some fancy two  current level driver for fun purposes.

There is also planar pcb trasformer design files but I will describe it later. Now I will only mention that PCB windings are designed with capacitance canceling method so transformer have virtually zero common mode noise (its standard Planar transformers biggest drawback). Design is also cost optimized, one complete transformer contains three 4-layer small PCB, so at JLCPCB cost is under 6$ for 2 sets.

There are also small PCB for digital isolators and relay connection (relay is driver from DCDC MCU).

PCB DESIGN FILES

Created in Altium Designer 21-22. Current version is newer than PCB that I have so its not verified. I'm constantly updating it. For Two main boards, DCDC and DCAC i've added PDFs with schematic and PCB.

https://github.com/KoRba88/Microinverter-V2-PCB


SOFTWARE GITHUB

https://github.com/KoRba88/Microinverter_V2.0_DCDC -Microinverter V2.0 DCDC Main software for main MCU

https://github.com/KoRba88/Microinverter_V2.0_DCAC - Microinverter V2.0 DCAC software for auxiliary microcontroller at HVDC side.

https://github.com/KoRba88/Microinverter_V2.0_GRID - Microinverter V2.0 GRID software for GRID side Volt,Current,HVDC measurement MCU

SOFTWARE

DCAC and GRID software is very simple (now). It gets trigger from HRTIM (synchronized with PWM period of inverter MOSFETS) to their ADC, make measurements and send via SPI data to the DCDC MCU. DCAC MCU also take care of Two level protection and power sequencing for gate drivers.

DCDC MCU get via SPI4-DMA Channel 2 interrupt request and starts whole loop. That ISR Drives whole converter loop. You can find it in DataSensing.C

#define DS_AcquisitionEvent DMA1_Channel2_IRQHandler

now the whole program start in 400WControl.c , after initialization void InitControl(ControlMode_t mode) and offset calibration u8 CalibrationControl() it gets to the open loop void ExecControlOpenLoop() or closed loop mode void ExecControl().

In ExecControl() there is a measurement data collection, processing and PWM execuiton.

Grid_Volt_q_d= DQ_PLL_Grid(Grid_Voltage); - make quadrature transformation of voltage

Output_qVd_Grid=(s16)(PLL_PID_Regulator(&DQ_PLL_PID,Grid_Volt_q_d)); PI Regulator for Vqd voltage

Calc_Theta_Grid(Output_qVd_Grid); - calculate frequency and phase angle for grid synchronization

Inverter_q_d=DQ_Filtering(DQ_Current_Inverter(qIalpha_Inverter,qIbeta_Inverter)); Current filtering

Actual_QD_Power =  DQ_Power_Estimation(Inverter_q_d); - Power estimation

switch (State_Control) is state machine that control all process

void CalcAndSetACComponents(SystStatus_t state) is a final function it sets a reference for direct and quadrature current (warning! direct and quadrature current are swapped in that software so no to be confused if you are familiar with control theory), make cross decoupling, reverse Park Transformation and send PWM signal.

Original firmware manual is also available there https://www.st.com/resource/en/user_manual/um1561-stevalisv003v1-firmware-user-manual-stmicroelectronics.pdf

Please feel free to comment.

[KoRba88]

Waveforms form Lf inverter inductor current



Current with zero-cross glitches and oscillations



Zoom with PWM form high side HF Mosfet. Sine goes up



Zoom with PWM form high side HF Mosfet. Sine goes down



From time to time sine loos better. Only glitches with no ostillations



Adding 1% of period to offset to the PWM signals i.e in void ExecControlOpenLoop()

qValpha_shifted_pos = ((u16)(SineWave+(TIMF_PERIOD)-330));

qValpha_shifted_pos = (u16)(330+(s16)(SineWave));

helps with oscillations to some degree, but cant reduce that huge glitch at zero cross.

I've simulated it in simulink but there is no oscillations. I was able to recreate similar oscillations only if I've delayed the zero cross LF MOSFETs signal relative to the HF zero cross edge. But my PWM signals are perfectly aligned.

[fourtytwo42]

IMOP the most likely reason for your zero-cross current spikes is poor phase compensation.
You have a voltage sense transformer, RC filter network and unknown software delays PLUS the delay inherent in the output LCL filter. It is quite possible to switch the H-bridge on to the new assumed polarity before the C portion of the LCL has in fact changed resulting in trying to force the capacitor prematurely to the opposite polarity.

This should be reasonably easy to prove with a suitable current probe by monitoring the LCL capacitor current.

I found it quite necessary to have a little deadtime around zero cross (H-bridge completely disabled) to allow things to settle, this had almost no detectable effect on THD. Of course this is with reference to my own design similar but not the same as yours.

[Miyuki]

Just an idea.
Why not run the output as hysteresis control without a fixed frequency.
It avoids all the possible stability issues. 

[KoRba88]

fourtytwo42 I don't have a voltage sense transformer (it s in old STm design). My all measurements is done synchronously by aux microcontroller (at GRID side) 2 ADCs. One ADC for Voltage, second for Current. Control loop works every other PWM cycle, so PWM/2 now loops takes 40 micro seconds and all calculations are done after 26 micro seconds.

Strange is that in ST app note they don't have any spikes. Strange is also that in closed loop controller takes a current for PWM generation but form scope looks like zero is switched not at zero current moment (but in zero voltage moment). Any settings in PI controller cant change that (tried to change Q Power reference and Quadrature current reference). Also tried to tune PI but it looks like its only changes stability in general but changes nothing near zero-cross event.

Regarding a dead time I have the same deadtime (500ns) between High and Low side High Frequency SiC Mosfets and Low Frequency Si Mosfets. And the HF PWM edge is alligned with LF grid frequency edge like in photo below. So when the polarization of sine is changing there is standard dead time here. Do you suggest that should I put more dead time in this moment?

[KoRba88]

Just an idea.
Why not run the output as hysteresis control without a fixed frequency.
It avoids all the possible stability issues.

I don't have an idea how it have to work. Do you have any paper on that? For grid connected inverters I saw 2 types of controllers. One which use Park (Direct-Quadrature) Transformations and regular PI controller, and second which use resonant PIR controller. (TI use it in https://www.ti.com/tool/TIEVM-HV-1PH-DCAC)  But both they have fixed frequency PWM.

[Miyuki]

Just an idea.
Why not run the output as hysteresis control without a fixed frequency.
It avoids all the possible stability issues.

I don't have an idea how it have to work. Do you have any paper on that? For grid connected inverters I saw 2 types of controllers. One which use Park (Direct-Quadrature) Transformations and regular PI controller, and second which use resonant PIR controller. (TI use it in https://www.ti.com/tool/TIEVM-HV-1PH-DCAC)  But both they have fixed frequency PWM.

This is not an AC inverter but D class audio amplifier, but it basically does the same thing.
Just use your desired waveform at the input and use output current instead of voltage
Not sure if this is the best paper
https://backend.orbit.dtu.dk/ws/portalfiles/portal/4386094/H%C3%B8yerby.pdf
It might be just a software change to try.
It can have some drawbacks but shall reproduce the input without distortion issues

[fourtytwo42]

OK I only have there schematic to go on as you have not published yours, I would be wary of all these extra mcu's, smells of more uncertainty, jitter and latency to me maybe 
From memory I think my completely deadtime is around 40uS either side of zero cross (80uS in total) and an enforced soft start of the modulator after ZX irrespective of the theoretical sine requirement just to keep the initial current under control.

Looking at your scope shot the modulation doesn't seem to be symmetrical around zero cross but more interestingly the duty cycle still seems to be ~2.5% immediately preceding it, again as if you are not phase locked properly and think your somewhere else in the sine before some other bit of code interrupts you unexpectedly to say the gridpolarity just changed 

In the early days many years ago I had a lot of this kind of stuff and it just took time and careful detective work to resolve it together with a few complete overhauls of the code 

I take it you also have a frequency locked loop and you don't have a permanent phase error as a result of being on the wrong frequency 

[KoRba88]

OK I only have there schematic to go on as you have not published yours, I would be wary of all these extra mcu's, smells of more uncertainty, jitter and latency to me maybe 
From memory I think my completely deadtime is around 40uS either side of zero cross (80uS in total) and an enforced soft start of the modulator after ZX irrespective of the theoretical sine requirement just to keep the initial current under control.

Schematics will be available when I will be able to force github to take the data (currently I'm getting some network disconnection error after uploading more files). What was your PWM Frequency? Don't get me wrong but I'm not buy the latency, uncertainty stuff since many of designs (i.e TI) use delta sigma modulators which they are slow and have bigger latency than my SAR ADC.

Looking at your scope shot the modulation doesn't seem to be symmetrical around zero cross but more interestingly the duty cycle still seems to be ~2.5% immediately preceding it, again as if you are not phase locked properly and think your somewhere else in the sine before some other bit of code interrupts you unexpectedly to say the gridpolarity just changed 

Yeah its clearly that is capacitive behavior and the current (yellow) is leading voltage (blue) by approx 10 degrees, but checked that by GPIO and disabled all interrupts (only one left that drives whole loop).

Also I've recorded all data that aux GRID MCU sends to main MCU on SD Card and the current and voltage looks similar to the scope waveforms.

[free_electron]

how do you get 25 year lifespan ?

[KoRba88]

how do you get 25 year lifespan ?

It's a goal. Since there is no electrolytic capacitors here and the ceramic caps have an margin, grid side is well protected so only failure could come from PCB solder joint cracks. Therefore with good PCB assembly it could have even a 50yrs lifespan.

[KoRba88]

I've connected a waveform generator to current and voltage sensing circuit trying to force a phase lag and lead between voltage and current for PI regulator to look if there is any change.

Tried 15deg lag and lead in closed loop mode. Resistive load. No difference. Maybe with inductive/capacitive load there will be some difference?

Increasing a dead time to 4uS (20% of PWM period) at zero-cross also changes nothing.

[fourtytwo42]

Tried 15deg lag and lead in closed loop mode. Resistive load. No difference. Maybe with inductive/capacitive load there will be some difference?

Errm is this actually a GRID TIED INVERTER or just an INVERTER ??
Some of your comments such as 15deg leg & lead would simply cause a true GTI to blow up trying to pump or short the grid!
Perhaps we could at least have a block diagram of your circuit and how you are trying to test it for clarity ?

[KoRba88]

Tried 15deg lag and lead in closed loop mode. Resistive load. No difference. Maybe with inductive/capacitive load there will be some difference?

Errm is this actually a GRID TIED INVERTER or just an INVERTER ??
Some of your comments such as 15deg leg & lead would simply cause a true GTI to blow up trying to pump or short the grid!
Perhaps we could at least have a block diagram of your circuit and how you are trying to test it for clarity ?

Currently is not connected to the grid. Connection the grid causes blow of MOSFETS or in best case only I was able to inject only few sine cycles (with 2khz current oscillations)

BUT algorithm is working in closed loop. I've connected 50Hz sine generator to the voltage measurement opamp so inverter thinks its connected to the grid. Current is measured in  from Lf (but in that test with current lead and lag I've detached signal form Lf and connected it to the channel 2 of the same waveform generator to check if any phase difference makes some changes). See attachment.

Also actually connection of current sensor and filter in schematics from ST at page 29 and 32 are wrong (I don't know why). They suggest that current sensor is connected after Lg inductor (page 29) or after LC filter and before Lg (page 32). But as it can be seen, current sensor is really connected after Lf (page 23).

https://www.st.com/resource/en/application_note/an4070-250-w-grid-connected-microinverter-stmicroelectronics.pdf

EDIT:
 I've tested step response of current sensing patch (from shunt resistor to aux ADC) and its look is 50 us and settle after 120 us after overshoot (ADC sampling and SPI transfer to the main MCU takes 10 us). As we saw before current is leading voltage by 800uS so looks current sensor shouldn't be a problem.

ST in thier microinverter have honywell CSLW6B5 sensor (3uS step response time) plus RC 1k+22nF = 80 us to 98% of final value.

[uer166]

Currently is not connected to the grid. Connection the grid causes blow of MOSFETS or in best case only I was able to inject only few sine cycles (with 2khz current oscillations)

BUT algorithm is working in closed loop.

If you have a real current mode controller, then it shouldn't blow up with the grid connected no matter what kind of waveform you're trying to inject into grid (lead or lag or whatever).

For real cycle by cycle current control you need a reasonably high bandwidth current sense, in the MHz range. If your main inductor current sense has a 120us delay, that is way, way too slow. That sense also wouldn't go only to an adc, but to some sort of comparator/DAC combo or two for hardware cycle-by-cycle limiting.

[KoRba88]

Currently is not connected to the grid. Connection the grid causes blow of MOSFETS or in best case only I was able to inject only few sine cycles (with 2khz current oscillations)

BUT algorithm is working in closed loop.

If you have a real current mode controller, then it shouldn't blow up with the grid connected no matter what kind of waveform you're trying to inject into grid (lead or lag or whatever).

For real cycle by cycle current control you need a reasonably high bandwidth current sense, in the MHz range. If your main inductor current sense has a 120us delay, that is way, way too slow. That sense also wouldn't go only to an adc, but to some sort of comparator/DAC combo or two for hardware cycle-by-cycle limiting.

Agree with first sentence, but what blows the MOSFETs is the oscillations of unstable loop and/or that zero cross spikes.

Dont agree with that the MHz range current sensor is needed. No grid inverter  in the world have that fast sensor. Current in grid have a 50-60Hz and current loops works at 1-5kHz max (1/10 -1/20 of switching frequency). See TI reference designs with sigma Delta modulators, barely 80kHz bandwidth for current sensing with high OSR filter, plus second filter with low OSR for overcurrent. Fast over current sensing is another thing. I have that realized by direct connection of shunt to comparator to cut off MOSFETs (but while testing I have increased the limits to see more disturbances)

[uer166]

Agree with first sentence, but what blows the MOSFETs is the oscillations of unstable loop and/or that zero cross spikes.

Dont agree with that the MHz range current sensor is needed. No grid inverter  in the world have that fast sensor. Current in grid have a 50-60Hz and current loops works at 1-5kHz max (1/10 -1/20 of switching frequency). Fast over current sensing is another thing. I have that realized by direct connection of shunt to comparator to cut off MOSFETs (but while testing I have increased the limits to see more disturbances)

No matter how shitty and unstable the outer control loops are, it shouldn't cause a power stage blowout. You always need a cycle by cycle current limit which requires a current sense in the order of 5-10x of your Fsw to catch the edges. What you call "direct connection of shunt to comparator" is usually the shunt->amplifier->cycle-by-cycle limit system that I'm talking about. It can be part of the main control loop like a hysteretic or peak mode current controller, but it doesn't have to, can be a bolt-on for average current mode, or even voltage mode.

I think until you implement full control of power stage inductor current (that works regardless of what's happening on grid/load side), you will not achieve reliability and prevent random mysterious FET failures.

[NiHaoMike]

Rather than try to sync a sine wave generator to the grid, what about use the grid voltage itself as the current reference for a current mode controller? Just scale it as needed to control the power, can be done either in digital or analog. I did just that in my senior design project using a digital potentiometer to adjust the loop gain.

[KoRba88]

Agree with first sentence, but what blows the MOSFETs is the oscillations of unstable loop and/or that zero cross spikes.

Dont agree with that the MHz range current sensor is needed. No grid inverter  in the world have that fast sensor. Current in grid have a 50-60Hz and current loops works at 1-5kHz max (1/10 -1/20 of switching frequency). Fast over current sensing is another thing. I have that realized by direct connection of shunt to comparator to cut off MOSFETs (but while testing I have increased the limits to see more disturbances)

No matter how shitty and unstable the outer control loops are, it shouldn't cause a power stage blowout. You always need a cycle by cycle current limit which requires a current sense in the order of 5-10x of your Fsw to catch the edges. What you call "direct connection of shunt to comparator" is usually the shunt->amplifier->cycle-by-cycle limit system that I'm talking about. It can be part of the main control loop like a hysteretic or peak mode current controller, but it doesn't have to, can be a bolt-on for average current mode, or even voltage mode.

I think until you implement full control of power stage inductor current (that works regardless of what's happening on grid/load side), you will not achieve reliability and prevent random mysterious FET failures.

Original ST design updates PWM only at period update so they are not using any cycle by cycle limit. Howeven In TI design https://www.ti.com/tool/TIEVM-HV-1PH-DCAC there are comparators connected directly to PWM to force PWM Tripping (I guess its simply cut PWM signal immediately after comparator triggers). In my design after comparator trigger (it have a 300ns delay only) it shut down PWM completely, but PWM tripping shouldn't be a problem to implement in STM32G4. Here we have inner current control loop where after park transformations the PI controller control the direct and quadrature current, and reference to that quadrature current is reactive power and for direct current is bus voltage.

Now I'm trying to add offset in reactive power PI reference to force current to be in phase with voltage. Without success yet.

In meantime in open loop mode I was able to set zero cross moment at zero current but this caused even more oscillations at zero-cross.

However all this things don't explain this sharp short current spikes (not oscillations)  at zero-cross polarity changeover. In literature I cant find any reference to that phenomena. What I observed that when I've not synchronized (see attached photo) the Low frequency mosfet signal with HF PWM edge (they switched at zero cross with approx 1us offset), and with big 4 us dead time in LF mosfets, that spike disappeared (but oscillations were bigger). So looks like at HF PWM when Sine is changing polarity and duty change from min to max the LF Mosfet have to be off. However that is strange since in every paper that I read and saw that PWM edged were perfectly alligned, even simulink simulations proves that it should work.

[KoRba88]

Rather than try to sync a sine wave generator to the grid, what about use the grid voltage itself as the current reference for a current mode controller? Just scale it as needed to control the power, can be done either in digital or analog. I did just that in my senior design project using a digital potentiometer to adjust the loop gain.

I'm not syncing anything with the grid. There is no grid at all here, I just connected waveform generator instead of grid (original ST design also have a DAC for grid simulation tests).

The reference for the current is the reactive power calculated by multiplying direct and quadrature voltages and currents (direct and quadrature current are swapped here). By reactive power control the phase angle between current and voltage should change.

And there are used to calculate signal that goes to reverse park transform to generate PWM

Code: [Select]

    Quadrature_Current_PID.Reference = (PID_Bus_Voltage(&BUS_Voltage_PID,Bus_Voltage));

    Direct_Current_PID.Reference = (PID_Reactive_Power(&Reactive_Power_PID, Actual_QD_Power.Q_Reactive));

    Output_qId_Inverter = (s16)(PID_DirectCurrent(&Direct_Current_PID, ((Inverter_q_d.qI_Direct))));

    Output_qIq_Inverter = ((s16)(PID_QuadratureCurrent(&Quadrature_Current_PID, ((Inverter_q_d.qI_Quadrature)))));

    CrossDecoupling_Control();

    RevPark_Circle_Limitation();

    Control_Volt_AlphaBeta= Rev_Park(Output_qIq_Inverter,Output_qId_Inverter);

[moffy]

Congratulations on your impressive amount of work. While I am not familiar with your output topology except in a general sense, I am familiar with the need to keep the output inductor, Lg, unsaturated, because it limits your di/dt. I did design a large SCR based supply that had to be linked with another supply, and we used a large 5mH air cored inductor, weighed over 200kg, and when fault currents of up to 2kA flowed, it still maintained its inductance and saved the SCRs. Could you use an air cored inductor for Lg? It wouldn't need to be 200kg or close to that, but it would not saturate.

[uer166]

Original ST design updates PWM only at period update so they are not using any cycle by cycle limit.

I've checked it and in Figure 13 of that design it seems that the L6390 itself acts as a cycle-by-cycle shutdown system with an embedded opamp, comparator, and latch all there in the driver. The feedback is coming from the FET sources in the low-side of the HF and LF half-bridges. Pls double check in case I misunderstood, but if that's true then all the designs that you linked have >MHz instantaneous inductor current sense, just implemented in different ways.

The way I've done this on STM32G4 use the PWM clear signal (after routing DAC+COMP output to it) in the advanced timers, or if you're using HRTIM then use it as an event. For now I'm convinced that at least in development you need this kind of fast realtime current limit in pure hardware.

[NiHaoMike]

I'm not syncing anything with the grid. There is no grid at all here, I just connected waveform generator instead of grid (original ST design also have a DAC for grid simulation tests).

The reference for the current is the reactive power calculated by multiplying direct and quadrature voltages and currents (direct and quadrature current are swapped here). By reactive power control the phase angle between current and voltage should change.

And there are used to calculate signal that goes to reverse park transform to generate PWM

Code: [Select]

    Quadrature_Current_PID.Reference = (PID_Bus_Voltage(&BUS_Voltage_PID,Bus_Voltage));

    Direct_Current_PID.Reference = (PID_Reactive_Power(&Reactive_Power_PID, Actual_QD_Power.Q_Reactive));

    Output_qId_Inverter = (s16)(PID_DirectCurrent(&Direct_Current_PID, ((Inverter_q_d.qI_Direct))));

    Output_qIq_Inverter = ((s16)(PID_QuadratureCurrent(&Quadrature_Current_PID, ((Inverter_q_d.qI_Quadrature)))));

    CrossDecoupling_Control();

    RevPark_Circle_Limitation();

    Control_Volt_AlphaBeta= Rev_Park(Output_qIq_Inverter,Output_qId_Inverter);

Seems overly complicated, in my senior design project I just divided down the mains voltage with a resistor divider, put that through a digital potentiometer to allow the microcontroller to adjust the gain, and then sent it to a common UC3843 which controls the PWM MOSFET. So basically a current output class D amplifier with the input connected to the output.

I'm now thinking that it probably would make more sense to take advantage of economies of scale and design the inverter to accept input from two panels (separate MPPT inputs) so that each inverter sits in the middle of two panels. Could possibly extend it even further to 3 or 4 panels but that would reduce compatibility with possible panel layouts.

[KoRba88]

Congratulations on your impressive amount of work. While I am not familiar with your output topology except in a general sense, I am familiar with the need to keep the output inductor, Lg, unsaturated, because it limits your di/dt. I did design a large SCR based supply that had to be linked with another supply, and we used a large 5mH air cored inductor, weighed over 200kg, and when fault currents of up to 2kA flowed, it still maintained its inductance and saved the SCRs. Could you use an air cored inductor for Lg? It wouldn't need to be 200kg or close to that, but it would not saturate.

Chokes are made of soft saturating sendust with about 3A capability. Currently I'm testing it with max 0.5A (even that glitch don't have 1A)

[KoRba88]

Original ST design updates PWM only at period update so they are not using any cycle by cycle limit.

I've checked it and in Figure 13 of that design it seems that the L6390 itself acts as a cycle-by-cycle shutdown system with an embedded opamp, comparator, and latch all there in the driver. The feedback is coming from the FET sources in the low-side of the HF and LF half-bridges. Pls double check in case I misunderstood, but if that's true then all the designs that you linked have >MHz instantaneous inductor current sense, just implemented in different ways.

The way I've done this on STM32G4 use the PWM clear signal (after routing DAC+COMP output to it) in the advanced timers, or if you're using HRTIM then use it as an event. For now I'm convinced that at least in development you need this kind of fast realtime current limit in pure hardware.

They don't use this comparator. In AN4070 their said that current is limited in software and comparator function is not used (and I have their original software so I checked that).

However I have that circuit and I'm using it for two level MOSFETs protection (I've described in 1st post what is two level MOSFETs protection).

Unfortunately no one (ST and TI) mention that is mandatory to avoid glitches at zero cross. Because its not the reason. If lack of cycle-by-cycle would have been the reason there should be more glitches at the ends of sine, not just one at polarity change.



That protection is only to avoid shorting of MOSFETs when you short inverter output.

[KoRba88]

I'm not syncing anything with the grid. There is no grid at all here, I just connected waveform generator instead of grid (original ST design also have a DAC for grid simulation tests).

The reference for the current is the reactive power calculated by multiplying direct and quadrature voltages and currents (direct and quadrature current are swapped here). By reactive power control the phase angle between current and voltage should change.

And there are used to calculate signal that goes to reverse park transform to generate PWM

Code: [Select]

    Quadrature_Current_PID.Reference = (PID_Bus_Voltage(&BUS_Voltage_PID,Bus_Voltage));

    Direct_Current_PID.Reference = (PID_Reactive_Power(&Reactive_Power_PID, Actual_QD_Power.Q_Reactive));

    Output_qId_Inverter = (s16)(PID_DirectCurrent(&Direct_Current_PID, ((Inverter_q_d.qI_Direct))));

    Output_qIq_Inverter = ((s16)(PID_QuadratureCurrent(&Quadrature_Current_PID, ((Inverter_q_d.qI_Quadrature)))));

    CrossDecoupling_Control();

    RevPark_Circle_Limitation();

    Control_Volt_AlphaBeta= Rev_Park(Output_qIq_Inverter,Output_qId_Inverter);

Seems overly complicated, in my senior design project I just divided down the mains voltage with a resistor divider, put that through a digital potentiometer to allow the microcontroller to adjust the gain, and then sent it to a common UC3843 which controls the PWM MOSFET. So basically a current output class D amplifier with the input connected to the output.

I'm now thinking that it probably would make more sense to take advantage of economies of scale and design the inverter to accept input from two panels (separate MPPT inputs) so that each inverter sits in the middle of two panels. Could possibly extend it even further to 3 or 4 panels but that would reduce compatibility with possible panel layouts.

Actually is mandatory by grid standards. In grid inverters you have to have a reactive power control also to increase active power production.
https://www.google.com/url?sa=t&source=web&rct=j&url=https://researchportal.hw.ac.uk/files/44448200/document_1_.pdf&ved=2ahUKEwi4mpL7-Nb3AhWGyosKHSB0ACwQFnoECDgQAQ&usg=AOvVaw2KKxt4owTThvi6KyTILSvZ

[moffy]

Chokes are made of soft saturating sendust with about 3A capability. Currently I'm testing it with max 0.5A (even that glitch don't have 1A)

What I mean is what happens when you blow your output devices when connected to mains? What are your fault currents then, I would guess more than 3A.

[KoRba88]

Chokes are made of soft saturating sendust with about 3A capability. Currently I'm testing it with max 0.5A (even that glitch don't have 1A)

What I mean is what happens when you blow your output devices when connected to mains? What are your fault currents then, I would guess more than 3A.

Yes, probably more but this will not solve the root cause of that zero-cross glitches, and they appear all the time, no matter if there is a no load or 40W light bulb or 200W . I have to eliminate them before connecting the inverter to the real grid.

Today I've checked all Vgs and Vds, and they look ok. Of course at zero cross Vds of LF mosfets are distorted (no matter of amount of dead time I set).

[NiHaoMike]

Actually is mandatory by grid standards. In grid inverters you have to have a reactive power control also to increase active power production.
https://www.google.com/url?sa=t&source=web&rct=j&url=https://researchportal.hw.ac.uk/files/44448200/document_1_.pdf&ved=2ahUKEwi4mpL7-Nb3AhWGyosKHSB0ACwQFnoECDgQAQ&usg=AOvVaw2KKxt4owTThvi6KyTILSvZ

You can do that by creating a delayed (by 1/4 of a cycle) version of the voltage signal and add or subtract it from the nondelayed signal.

[KoRba88]

Actually is mandatory by grid standards. In grid inverters you have to have a reactive power control also to increase active power production.
https://www.google.com/url?sa=t&source=web&rct=j&url=https://researchportal.hw.ac.uk/files/44448200/document_1_.pdf&ved=2ahUKEwi4mpL7-Nb3AhWGyosKHSB0ACwQFnoECDgQAQ&usg=AOvVaw2KKxt4owTThvi6KyTILSvZ

You can do that by creating a delayed (by 1/4 of a cycle) version of the voltage signal and add or subtract it from the nondelayed signal.

That would be very noisy and unstable.

Now I'm creating orthogonal signal of the voltage which is delayed by 1/4 (90deg) but that together with normal voltage is routed to Park transformation and to PI regulator, then to integrator PLL to create angle theta and frequency for grid synchronization. But probably the part responsible for Q control don't work properly because reactive power don't change phase angle at my command.

[jbb]

Late to the party on the zero crossing bump… the use of a slow leg (Si devices) and fast leg (SiC devices) does mean you get quite a big bump when the slow leg switches.

This is effectively a large common mode signal, and it will couple through stray capacitances to ground. If you’re using a big DC bench supply for the DC link you might have a big stray capacitance inside which is subjected to a 400V swing when the slow leg fires.

Sorry I don’t have time to dig in properly, you may already know this, but the switching of the slow Si leg is determined not by zero crossing of the AC line voltage but instead by the zero crossing of the PWM reference signal. These likely have a bit of a phase offset.

On component destruction: I recommend adding some overcurrent and over voltage trips (gate all FETs off and open relay) to your test software. That way an unstable loop will cause a trip rather than a boom. In a past prototype I even deployed analog comparators and logic chips so it would trip even if the software was bolloxed.

In that previous project, I found that you can get quite a good idea of the current control behaviour by shorting the ‘AC line’ terminals and setting the software to generate its own 50Hz reference.

[uer166]

That's a very good point about the extreme common mode swings. I've designed an experimental boost inverter and decided to use the equivalent of 2 HF half-bridges, each with their own inductor. That makes for essentially a split phase output without any high frequency CM voltages, and it plays nice with anything.

IMO swinging the CM output that fast and at that high of a voltage is never a good idea unless you have taken extreme isolation measures and keep the capacitance low between primary and secondary.

Maybe in next rev you can adapt it to output 2 phases instead of one, and remove the low frequency leg entirely..

[KoRba88]

Late to the party on the zero crossing bump… the use of a slow leg (Si devices) and fast leg (SiC devices) does mean you get quite a big bump when the slow leg switches.

This is effectively a large common mode signal, and it will couple through stray capacitances to ground. If you’re using a big DC bench supply for the DC link you might have a big stray capacitance inside which is subjected to a 400V swing when the slow leg fires.

Sorry I don’t have time to dig in properly, you may already know this, but the switching of the slow Si leg is determined not by zero crossing of the AC line voltage but instead by the zero crossing of the PWM reference signal. These likely have a bit of a phase offset.

On component destruction: I recommend adding some overcurrent and over voltage trips (gate all FETs off and open relay) to your test software. That way an unstable loop will cause a trip rather than a boom. In a past prototype I even deployed analog comparators and logic chips so it would trip even if the software was bolloxed.

In that previous project, I found that you can get quite a good idea of the current control behaviour by shorting the ‘AC line’ terminals and setting the software to generate its own 50Hz reference.

DC link is supplied internally by transformer isolated LLC stage of microinverter. That transformer have some stray capacitance since its winding are interleaved however I've added Y Cap connecting both grounds to shunt HF current noise.

Currently all MOSFETs are Si. There is no spurious turn on from miller and dv/dt product at slow and fast leg.

For protection there are low side comparators for each leg (and they works fast, 300ns from detection to shut off)

For inline current sensing there is a comparator just after the first opamp at inductor shunt. However here I have a large noise from LLC converter at 2x switching frequency (140kHz x2) so I have added more filtering to that and its not as fast. However its shouldn't be a problem since 1mH grid inductor are slowing down the current so it should works that way.

Regarding phase offset, there will be always some but shouldn't be no more than 2x of switching frequency, so max 40 us, not 500-800 us. That is definitely comes from LC filter.

[KoRba88]

That's a very good point about the extreme common mode swings. I've designed an experimental boost inverter and decided to use the equivalent of 2 HF half-bridges, each with their own inductor. That makes for essentially a split phase output without any high frequency CM voltages, and it plays nice with anything.

IMO swinging the CM output that fast and at that high of a voltage is never a good idea unless you have taken extreme isolation measures and keep the capacitance low between primary and secondary.

Maybe in next rev you can adapt it to output 2 phases instead of one, and remove the low frequency leg entirely..

Bipolar modulation require 2 inductors (equal) but is bad for THD and require higher switching frequency so loses will be bigger.

Actually that LF 50Hz reduces CM significantly since is low frequency and that Si mosfets have about 50nS turn on and 30ns turn off so its max 13V/ns, not to high.  SiC MOSFETs have a less than 10ns turn off and when I've tested them they worked fine without any CM noise problems or miller gate turn on. To reduce voltage swing only way is go to the Three Level (or more) topology inverter.

See https://ieeexplore.ieee.org/document/7930777

The authors of that paper also say something about zero-cross distortions
 
"Also at the zero crossing of the output voltage there will be some distortion in the hybrid modulation due to the discontinuous change in the modulation state (when output voltage changes from positive to negative) compared with unipolar or bipolar modulation which is continuous and do not have zero crossing problems."

However distortion =/= huge glitch. Actually after some PI tuning I've almost zero oscillations at one side of sine, and some at the other side. But glitches are still present.

[uer166]

Bipolar modulation require 2 inductors (equal) but is bad for THD and require higher switching frequency so loses will be bigger.

I admit I read your paper but I don't fully understand why the THD would be tied to which topology. The PID/DQ/2p2z/whatever control scheme is probably the biggest factor for THD. It's more or less what I tried here: https://www.eevblog.com/forum/projects/experimental-48v-gt120vac-60hz-inverter/msg3401984/. You basically have 2 independent sync buck converters, that would have same THD/noise contribution as the one you have already. Yes, you will have slightly higher losses, but IMO it's worth the transient/short protection (all silicon is behind your big inductors), and good control of CM noise. I've had serious issues once of that kind of CM coupling into control circuitry and faulting out the converter.

One issue might be that the LF HB output is swinging with really hard edges at 60Hz, which will couple through your Y-cap across the transformer into your input (e.g. if the input has same reference/ground as your output in your test).. Maybe try removing that Y-cap and instead let your transformer handle the output CM swing?

[NiHaoMike]

That would be very noisy and unstable.

Why? You're just putting the samples through a FIFO buffer so that it ends up delayed by 1/4 of a mains cycle. It only has as much noise as the input, which is easy to reduce to very low levels given you're starting with 120V or 240V.

[Phoenix]

I'm not syncing anything with the grid.

Now I'm creating orthogonal signal of the voltage which is delayed by 1/4 (90deg) but that together with normal voltage is routed to Park transformation and to PI regulator, then to integrator PLL to create angle theta and frequency for grid synchronization. But probably the part responsible for Q control don't work properly because reactive power don't change phase angle at my command.

What are you connecting the AC terminals to? A resistive load? Looks like a light bulb.

You will only be able to control the current phase angle relative to the voltage if you're connected to a stiff voltage source. Otherwise your current angle will be determined by the RLC's of the load - adding a reactive command will shift the phase relative to your internal phasor but externally the observed voltage-current phase will always remain the same.

[Phoenix]

Actually after some PI tuning I've almost zero oscillations at one side of sine, and some at the other side. But glitches are still present.

From your earlier oscillograms it looks like the minimum effective pulse width is asymmetrical for short turn on and turn off pulses around the polarity switch. Perhaps you're getting more glitch in the "small on pulse" region because it requires more duty cycle to get an effective gate pulse.

Someone earlier mentioned putting in some blanking time - ideally you need both phase legs to switch polarity at exactly the same time which it seems you have achieved pretty well.

This issue may have a different distortion characteristic when you're running reactive current because the voltage zero crossing will not longer be the current zero crossing. This may also be what is happening because the inverter is supplying the reactive current for the filter capacitors.

[Phoenix]

That would be very noisy and unstable.

Why? You're just putting the samples through a FIFO buffer so that it ends up delayed by 1/4 of a mains cycle. It only has as much noise as the input, which is easy to reduce to very low levels given you're starting with 120V or 240V.

A well designed PLL will remove grid voltage distortion from the current reference signal. Once you have the synchronous value of phase you can simply use sine and cosine to generate the direct and quadrature current components. You can also correct for any inherent phase offset in your algorithm (or sense network) by adding or subtracting a little from theta.

[KoRba88]

That would be very noisy and unstable.

Why? You're just putting the samples through a FIFO buffer so that it ends up delayed by 1/4 of a mains cycle. It only has as much noise as the input, which is easy to reduce to very low levels given you're starting with 120V or 240V.

A well designed PLL will remove grid voltage distortion from the current reference signal. Once you have the synchronous value of phase you can simply use sine and cosine to generate the direct and quadrature current components. You can also correct for any inherent phase offset in your algorithm (or sense network) by adding or subtracting a little from theta.

Good point Phoenix. Moreover GRID itself is noisy and unstable so you have to have some filtering and fast reaction time. This is not trivial task since filtering and fast reaction time are a contradictions in general meaning. Park transformations and PI acts together as a fast filter so disturbances form a grid can be reduced to some degree.

[KoRba88]

Actually after some PI tuning I've almost zero oscillations at one side of sine, and some at the other side. But glitches are still present.

From your earlier oscillograms it looks like the minimum effective pulse width is asymmetrical for short turn on and turn off pulses around the polarity switch. Perhaps you're getting more glitch in the "small on pulse" region because it requires more duty cycle to get an effective gate pulse.

Yeah but that can be due to a little offset in measured current that is feed to PI regulator. Its about 0.01% of the signal amplitude but It could have an impact.

[KoRba88]

I'm not syncing anything with the grid.

Now I'm creating orthogonal signal of the voltage which is delayed by 1/4 (90deg) but that together with normal voltage is routed to Park transformation and to PI regulator, then to integrator PLL to create angle theta and frequency for grid synchronization. But probably the part responsible for Q control don't work properly because reactive power don't change phase angle at my command.

What are you connecting the AC terminals to? A resistive load? Looks like a light bulb.

You will only be able to control the current phase angle relative to the voltage if you're connected to a stiff voltage source. Otherwise your current angle will be determined by the RLC's of the load - adding a reactive command will shift the phase relative to your internal phasor but externally the observed voltage-current phase will always remain the same.

Yeah, resistive load. I'll try with RL load (i.e bulb and 1mH toroid) to tune PI controller.

Now the plan is connect inverter to the grid with fast 1A fuses on both zero and live wire. Then start with switching off, just measure. Then LF leg only, then try the whole thing with HF PWM.

[NiHaoMike]

Good point Phoenix. Moreover GRID itself is noisy and unstable so you have to have some filtering and fast reaction time. This is not trivial task since filtering and fast reaction time are a contradictions in general meaning. Park transformations and PI acts together as a fast filter so disturbances form a grid can be reduced to some degree.

Wouldn't making it somewhat unstable help with anti islanding? Or are you intending for it to connect to an ATS to be able to switch to off grid operation and therefore need it to be able to operate in a stable manner?

[Siwastaja]

Let's be straight:

Cycle-by-cycle current limit is the first thing you do. Unless your target is some $0.01 chinesium gadget where you can't afford the sense bandwidth.

Everything else is secondary to that.

It might be that at some point, this cycle-by-cycle limit never triggers, but it is the feature which prevents inductors from saturating and semiconductor switches from blowing up, for whatever reason.

You really can't rely on your control loop and PWM control always functioning in such way that inductor saturation just does not happen. Real world is full of edge cases. Having an unexpected transient as a result is OK; blowing up the power devices is not. Because MOSFETs blow up in microseconds, you need active protection that can react within those microseconds. In other words: too much current -> turn it off quickly.

Once you have this, prototyping and developing the control loops becomes actually possible, as any mistake here can't blow up anything.

[KoRba88]

Let's be straight:

Cycle-by-cycle current limit is the first thing you do. Unless your target is some $0.01 chinesium gadget where you can't afford the sense bandwidth.

Everything else is secondary to that.

It might be that at some point, this cycle-by-cycle limit never triggers, but it is the feature which prevents inductors from saturating and semiconductor switches from blowing up, for whatever reason.

You really can't rely on your control loop and PWM control always functioning in such way that inductor saturation just does not happen. Real world is full of edge cases. Having an unexpected transient as a result is OK; blowing up the power devices is not. Because MOSFETs blow up in microseconds, you need active protection that can react within those microseconds. In other words: too much current -> turn it off quickly.

Once you have this, prototyping and developing the control loops becomes actually possible, as any mistake here can't blow up anything.

Did you read my previous posts?I have even more advanced protection called two level MOSFETs turn off circuit with shut down MOSFETs completely within 1us. It's verified but at first time when I tried to connect inverter to the grid I had to increase filtering here (and therefore reaction time) and due to some false triggering due to noise at HVDC bus with was triggering OC at inductor comparator. I have to put inductor to create LC filter on HVDC bus to filter out that noise and then the protection will work as designed.

[jonpaul]

anti-islanding is required by most electrical codes.

A permit, utility firm connection and approval as well.

A liscenced électricien required to connect

DIY installation will not be compliant, void the properties insurance and may be dangerous.

I would seek advice of local firms, also the electrician forums and Mike Holt forums of electrical inspectors.

Be safe,

bon courage

Jon

[uer166]

Did you read my previous posts?I have even more advanced protection called two level MOSFETs turn off circuit with shut down MOSFETs completely within 1us. It's verified but at first time when I tried to connect inverter to the grid I had to increase filtering here (and therefore reaction time) and due to some false triggering

If that system worked properly then you wouldn't have blown the FETs as soon as the grid got connected. Are you 100% sure the triggering was indeed false and not a real over-current event? I've had cases where I thought I had false trips, and then tried to relax/disable the OC protection, and it promptly blew up some gate drives due to it being a real overcurrent event.

I'd do some minimal single and double pulse tests in known conditions to test the overcurrent protection, before even messing with the control loop. Just create a 1 or 2-pulse train into the gate driver to generate a ramp and peak current that should trip the OC, and see if it does.

Post the inductor current in those pulse tests, would be interesting to see.

[NiHaoMike]

anti-islanding is required by most electrical codes.

A permit, utility firm connection and approval as well.

A liscenced électricien required to connect

DIY installation will not be compliant, void the properties insurance and may be dangerous.

I would seek advice of local firms, also the electrician forums and Mike Holt forums of electrical inspectors.

A workaround would be to make an "educational" version that connects via a low voltage transformer, the main intent would be to make it safer to tinker with. If you could find a ready made box that has the transformer connected to an AC cord and exposes the low voltage secondary on a connector (sadly getting harder and harder to find when switching supplies have largely replaced them), the user won't even have to do anything with the mains other than plugging the transformer in.

[KoRba88]

Did you read my previous posts?I have even more advanced protection called two level MOSFETs turn off circuit with shut down MOSFETs completely within 1us. It's verified but at first time when I tried to connect inverter to the grid I had to increase filtering here (and therefore reaction time) and due to some false triggering

If that system worked properly then you wouldn't have blown the FETs as soon as the grid got connected. Are you 100% sure the triggering was indeed false and not a real over-current event? I've had cases where I thought I had false trips, and then tried to relax/disable the OC protection, and it promptly blew up some gate drives due to it being a real overcurrent event.

I'd do some minimal single and double pulse tests in known conditions to test the overcurrent protection, before even messing with the control loop. Just create a 1 or 2-pulse train into the gate driver to generate a ramp and peak current that should trip the OC, and see if it does.

Post the inductor current in those pulse tests, would be interesting to see.

Yep, it was false triggering since it occurred as soon as I turned on LLC stage without even turning on switching at DCAC stage so without any load on inverter inductor. I have independent power supplies here so I can turn on supply for inductor current sensing without turning ON the LLC stage. Moreover OC pulses have a double switching frequency (positive and negative polarity from voltage doubler) of LLC stage.

[KoRba88]

anti-islanding is required by most electrical codes.

A permit, utility firm connection and approval as well.

A liscenced électricien required to connect

DIY installation will not be compliant, void the properties insurance and may be dangerous.

I would seek advice of local firms, also the electrician forums and Mike Holt forums of electrical inspectors.

Be safe,

bon courage

Jon

anti-islanding is implemented, simple as a thresholds of frequency and voltage driven by local grid requirements

Moreover the plan is to make commercial version of that microinverter and make a certification.

[Phoenix]

I was thinking this was a great personal project... You have a long long way to go to become compliant. And need some really deep pockets.

What compliance region/country are you aiming for?

(I do design grid connect inverters for a living and have put one through AS4777. 2).

[KoRba88]

I've played a bit with dead time and minimum pulse width.

When I reduced the dead time near very low and very large pulses (but not to large, ie 96-98% of Dmax), the distortions at zero cross were smaller. Also when I put the limit to min pulse value, the distortion were smaller. With outsynchronizing LF leg the glitch disappeared but oscillations were bigger.

The effect was similar to that in this app note from TI "How to Reduce Current Spikes at AC Zero-crossing for Totem-pole PFC" . The modulation for this PFC is the same.

Moreover they completely removed the spike around zero and oscillations! Looks like I was close to achieve that.

https://www.ti.com/lit/slyt650

I will adopt that algorithm to see the effects.

My LF MOSFETs have also fast recovery diodes and fairly small output capacitance so it should be easier to achieve that.

[KoRba88]

I was thinking this was a great personal project... You have a long long way to go to become compliant. And need some really deep pockets.

What compliance region/country are you aiming for?

(I do design grid connect inverters for a living and have put one through AS4777. 2).

Polish market but now it's just only a wish rather than serious idea.

For now the plan is that in the end the HW will be open source and end user will pay only licence for the software.

[KoRba88]

I've implemented current spike reduction algorithm. Currently its only for open loop. For closed loop it will be not so easy.

Firstly I;'ve tried with ST version ( https://www.st.com/resource/en/user_manual/um2792-getting-started-with-the-stevaldpstpfc1-36-kw-pfc-totem-pole-with-inrush-current-limiter-reference-design-stmicroelectronics.pdf) since it was easier, to implement but result was poor. Spike was reduced but there was still huge oscillations.

TI approach although complicated in MCU implementation  is superior and there is significant spike reduction. My version of algorithm (i.e soft start) is not perfect yet but it works. That additional tiny pulses around zero cross do the job, discharging MOSFET capacitance.

The waveform is not smoothed as previously because I've reduced the current sensor filter so now is 5 times faster (10 us) also its only 350 mA here, at full 2A current will look even better.

[lyxer]

where and how to buy the transformer?

[jonpaul]

transformers are DIY, beware all ferrite cores are very delayed delivery 38..80 weeks

No off the shelf transformers

j

[ManniW]

I'm wondering: How much can this design be tuned for efficiency? If GaN-FETs are used they have a very low RDSon aswell as a very low switching time and charge, so losses could be reduced significantly. Also the choice of diodes could probably be improved a little, increasing the total efficiency even further. Is the LLC Tank really more efficient than the original design? They calculated a pretty good efficiency and using other diodes/FETs it could be bumped up to over 97% using the formulas in the AppNote.

Using the HERIC inverter design on the output side could give another efficiency bump (but it will make the software more complicated, but only slightly).

[Ali Elsayed]

hello, can anyone kindly advise ? can i make the original inverter but only change the DCAC side MOSFETs by GaN FETs and change the gate drivers ? and would it work without problems ? i'm not experienced, any help would be much appreciated

[Siwastaja]

hello, can anyone kindly advise ? can i make the original inverter but only change the DCAC side MOSFETs by GaN FETs and change the gate drivers ? and would it work without problems ? i'm not experienced, any help would be much appreciated

Of course not. This is state-of-art which requires months and months of design work from top-1% power electronics engineer to even build a prototype, and years for a complete product. Buy a ready made inverter, they are easily available.