Opinion about this bga desing. Uncovered vias between pads?

[DavidAlfa]

We're having some issues with customer-designed pcb.
Few bgas are failing, either due ball migration (short), not properly soldered (ball sit on the pad but not soldered ), others show nothing strange under x-rays.

They use a weird flux, not even close to Amtech, seems like a semi-liquid rosin flux with terrible obnoxius fumes that will make you choke out.
I decided to take one of the ones tagged as scrap / unrepairable.
Well, I'm not expert but those uncovered vias look like sh** asking for trouble very loudly!
Just to my own curiosity, I reballed it using my $7 chinese bga kit + $22 858D hot air station.
My other tests (fbga 0.3mm ball dram ic, 0.25mm emmc) looked perfect under x-rays.

I'm not telling I'm better than them, just for curiosity.
The mcu itself may be damaged after all (Bad ADC reading in one channel).
Tomorrow we'll see how it look under the rays.
These boards are getting seriously tanned

[ataradov]

What is even going on here? Untented vias are a non-starter, of course. But why do they have some pads without holes? Are half of the vias plugged and others are not?

[PCB.Wiz]

What is even going on here? Untented vias are a non-starter, of course. But why do they have some pads without holes? Are half of the vias plugged and others are not?

I wondered that, but I think they've just done a break-out footprint, and have used via in pad routing for those pins.
I notice a couple of much smaller holes appear on vias to the left ?

[T3sl4co1l]

Seems like there's two sizes of hole used, and both of them erratically are plating shut at the board face.  Seems like the fab quality is matched only by the layout design quality..!

Tim

[langwadt]

what on earth where they thinking?

[shakalnokturn]

what on earth where they thinking?

Were they thinking (at all)?

[DavidAlfa]

These were my thoughts, and yeah, I also doubt this is a fab problem, but 100% originally designed this way.
Amazingly, only about 2% are failing! 

[SiliconWizard]

This layout is quite funky. I suspect they may have defined a number of different vias in the project, and then selected either of them without much care while adding vias, as long as they fitted. It may have not been too obvious in the layout editor itself. They should have had a look at the Gerber though.

[DavidAlfa]

After reballing myself, checked the x-rays and surprise!
Two balls were sucked by nearby vias. Rest were perfect.
Not my problem. Engineers are ok with that, not my job, I just gave it a try at my own.

[ArdWar]

Why didn't they use pad in via if they already went such length to get plugged vias? Did I miss something obvious here?

Either failure to recognize a problem or failure to cost optimize, neither feels like a good impression for the designer.

[DavidAlfa]

Yeah, after several years I came to the conclusion I either work for Nike, or my company is sponsored by them, there're too many "Just do it" !

[twospoons]

Its probably just a mix of blind and thru vias. But leaving them uncovered was silly.

[DavidAlfa]

Yes, after analyzing the pinout, it's a net class thing.
Power pins (VDD, VSS) have via holes, signal ones (GPIO) doesn't.