EEVblog Electronics Community Forum
Electronics => Projects, Designs, and Technical Stuff => Topic started by: kcs on October 19, 2014, 01:03:15 am
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Let's say you have an IC, which has two Vdd pins. What would be the optimal place for the large value capacitor, which will act as a storage tank?
My intuition says that I should go with (3). I am using a 2-layer board.
(http://i.snag.gy/uiq0j.jpg)
Btw, decoupling caps are used, but they are not displayed in this simplified schematic.
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Well it dpeends on what sort of device it is.
Digital? No problem just slap a 0.1uf within 1-2 inches.
16bit ADC? A bit more complex.
Now this is for local bypassing. You want more filtering upstream depending on what other stuff you have and how you are powering it.
On 2layer boards generally you want to have a cap right at each power pin with a via to ground/power or however you have it set up.
On 4layer and up I just rely on internal planes, and put the caps as close as feasible
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Anything with that kind of package is not critical anyways IMO. The large value capacitor (WHAT value?) can be put anywhere, then whack a 0.1uF near each VDD pin. That's SOP. Unless, of course, it isn't the same voltage. Is one "analog" and the other "digital"? Then as marshallh said it's a bit more complex, you might want to put a LC filter on there, maybe knock out a switcher's frequency or something like that.
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https://www.sigcon.com/Pubs/news/9_07.htm (https://www.sigcon.com/Pubs/news/9_07.htm)
http://electronics.stackexchange.com/questions/74509/how-to-place-decoupling-capacitor-in-four-layer-pcb (http://electronics.stackexchange.com/questions/74509/how-to-place-decoupling-capacitor-in-four-layer-pcb)
http://www.maximintegrated.com/en/app-notes/index.mvp/id/5100 (http://www.maximintegrated.com/en/app-notes/index.mvp/id/5100)
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It is BT module. I will be using 100uF tantalum cap.
1st VDD: Supply for RF power amplifier and low noise amplifier of the module
2nd VDD: Supply for on-board uC and flash memory
marshallh, I have followed the guide on placing decoupling caps in your second URL. In question is that bigger tantalum cap, but from your answers it seems I do not need to worry about its place.
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It is BT module. I will be using 100uF tantalum cap.
1st VDD: Supply for RF power amplifier and low noise amplifier of the module
2nd VDD: Supply for on-board uC and flash memory
marshallh, I have followed the guide on placing decoupling caps in your second URL. In question is that bigger tantalum cap, but from your answers it seems I do not need to worry about its place.
Ah, all the important decoupling is already done on the module. That 100uF can indeed be placed anywhere that fits. Use ceramic. Tantalum is like '80s big hair.
http://www.digikey.ca/product-detail/en/GRM31CR60J107ME39L/490-4539-1-ND/1033313 (http://www.digikey.ca/product-detail/en/GRM31CR60J107ME39L/490-4539-1-ND/1033313)
Check your temperature derating though.
Does the module datasheet provide a recommended design? FYI, those modules sometimes have vias and traces on their bottom sides, do you have a keepout to respect on your PCB?
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If you use tantalum there are four rules to keep it reliable. 1) derate the voltage to about 60% maximum. 2) insure that there's a current limiting resistor of between 0.1 and 3 ohms per volt, the higher the better. 3) keep the temperature low. 4) use a ceramic!
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Ah, all the important decoupling is already done on the module.
It could be the case. I have checked its evaluation kit, and indeed there are no de-coupling caps for those VDD pins.
Use ceramic. Tantalum is like '80s big hair.
Why? I see tantalum caps used all over the place, in new designs as well. Even evaluation kit for that module uses some tantalum caps ::)
Does the module datasheet provide a recommended design?
Yes, but it is for 4-layer board.
FYI, those modules sometimes have vias and traces on their bottom sides, do you have a keepout to respect on your PCB?
Yes, this module does have them as well. But I am not sure what do you mean by "keepout to respect on your PCB"?
Conrad Hoffman, thank you for an advice. I was aware of (1) and (3), but I did not know about (2).
I was about to use something like this: http://www.digikey.ca/product-detail/en/T520C107M010ATE025/399-9775-1-ND/3724774 (http://www.digikey.ca/product-detail/en/T520C107M010ATE025/399-9775-1-ND/3724774)
Its datasheet says: "(...) captures the best features of multilayer ceramic, aluminum electrolytic, and proven solid tantalum technology". So it sounds like it is the crème de la crème within capacitors.
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Modern tants are a lot better than the old ones, but still they are basically dense, flammable material jammed into a small space and ready to go off.
The two things that do in tantalums (and thus your entire PCB) are
1. Current spikes (di/dt)
2. Over-voltage
You can mitigate both by derating voltage by 3x, e.g if you have a 3.3v system, use at least a 10V rated tantalum (and a 16 or 25v if you can afford to)
To limit current changes put a small ferrite or resistor in series, calculate to make sure it will not negatively affect power delivery.
Modern ceramics (MLCC) are getting very dense and cheap. They won't blow up, instead they typically fail open (Though I have some that've failed short-ouch) In addition they have much, much lower ESR, in fact some are so good that putting them onto LDO outputs will cause oscillation.
MLCCs should have voltage derated as well but for another reason - voltage bias causes the effective capacitance to drop like a rock.
E.g. your 10V, 22uF cap will become a 10uF cap if you put 5 volts on it (just a guess but gives you an idea)
In addition ceramics exhibit a piezo effect, this is mostly only an issue with very small-valued caps (picofarads) with NPO-C0G dielectrics. Mechanical torsion (twisting) causes the cap to produce small spikes of energy which could be problem if it was part of a critical feedback loop or something
This is all much more information than you need to know for your particular case. If I were designing it I'd put a 10uF MLCC cap in parallel with a 100uF aluminum electrolytic for the module.
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VDD pins are exactly 50% of the problem, where are the grounds?
If this is 4 layer and you're dropping everything to vias as near to the pins as practical, it makes no difference whatsoever; the plane is doing the job first.
If you mean bulk caps, it makes even less difference as the higher ESR means they have little to no effect on local supply impedance. Think of them not as bulk storage but rather as damping resistance, to be spread out at strategic locations (usually end points, and around inductors) to dampen resonances between traces, smaller bypass caps, and planes.
Tim
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marshallh, thank you for such an in-depth answer. Just out of curiosity, why are tantalum caps used these days, if there are better alternatives? Knowing that they are relatively expensive, why do manufacturers choose to use them?
MacBook Pro teardowns:
https://d3nevzfk7ii3be.cloudfront.net/igi/WXGTXbIQoUx646jF.huge
https://d3nevzfk7ii3be.cloudfront.net/igi/n2TrniSjqkvPPsuc.huge
https://d3nevzfk7ii3be.cloudfront.net/igi/Ns4fKV3jx5kTllRa.huge
https://d3nevzfk7ii3be.cloudfront.net/igi/AG3pwEJMI5xJ6Vcd.huge
VDD pins are exactly 50% of the problem, where are the grounds?
Half of module pins are GND pins. I use top and bottom solid polygon pours as GND. I stitch them with multiple vias in different places.
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marshallh, thank you for such an in-depth answer. Just out of curiosity, why are tantalum caps used these days, if there are better alternatives? Knowing that they are relatively expensive, why do manufacturers choose to use them?
MacBook Pro teardowns:
https://d3nevzfk7ii3be.cloudfront.net/igi/WXGTXbIQoUx646jF.huge
https://d3nevzfk7ii3be.cloudfront.net/igi/n2TrniSjqkvPPsuc.huge
https://d3nevzfk7ii3be.cloudfront.net/igi/Ns4fKV3jx5kTllRa.huge
https://d3nevzfk7ii3be.cloudfront.net/igi/AG3pwEJMI5xJ6Vcd.huge
VDD pins are exactly 50% of the problem, where are the grounds?
Half of module pins are GND pins. I use top and bottom solid polygon pours as GND. I stitch them with multiple vias in different places.
Who knows? Inertia?
Anyways, are you sure you can pour ground under the module? Sometimes there's a keepout to respect if there's an internal antenna.
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Those caps looks like Poscaps, tantalums with a polymer electrolyte, from Panasonic.
Datasheet
http://industrial.panasonic.com/www-data/pdf/AAA8000/AAA8000CE7.pdf (http://industrial.panasonic.com/www-data/pdf/AAA8000/AAA8000CE7.pdf)
Application/Marketing info
http://industrial.panasonic.com/www-data/pdf/AAA8000/AAA8000PE28.pdf (http://industrial.panasonic.com/www-data/pdf/AAA8000/AAA8000PE28.pdf)
At least they seem to be a better option than ceramics in some applications
- Better ESR than tantalums but worse than ceramics
- Capacitance seem to be stable even during voltage bias
- More capacitance in the same volume. 330uF in D (7343) package
- No piezoelectric effect, i.e. will not create noise due to ripple currents
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Tantalum are good for bulk (e.g., filtering switcher ripple) and damping (well controlled ESR). Ceramic isn't good for bulk because it's, well, a bit bulky, and relatively expensive for its size (not that tantalum is extremely cheap either, but apparently the size and cost tradeoffs are enough). And the low ESR means unfortunate resonances at odd frequencies; you can dampen this with resistors, but then you lose space (and maybe some cost) to area and assembly time.
Tim
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Those caps looks like Poscaps, tantalums with a polymer electrolyte, from Panasonic.
Datasheet
http://industrial.panasonic.com/www-data/pdf/AAA8000/AAA8000CE7.pdf (http://industrial.panasonic.com/www-data/pdf/AAA8000/AAA8000CE7.pdf)
Application/Marketing info
http://industrial.panasonic.com/www-data/pdf/AAA8000/AAA8000PE28.pdf (http://industrial.panasonic.com/www-data/pdf/AAA8000/AAA8000PE28.pdf)
At least they seem to be a better option than ceramics in some applications
- Better ESR than tantalums but worse than ceramics
- Capacitance seem to be stable even during voltage bias
- More capacitance in the same volume. 330uF in D (7343) package
- No piezoelectric effect, i.e. will not create noise due to ripple currents
Agreed, very low voltage cans are probably polymer. There are many brands (e.g. Oscons) but they're generically just polymers. I don't like genericized brand names...
Anyway, polymers are essentially film caps with low voltage ratings and comparable energy density: the ESR is low (not as low as ceramic, but low enough that you'll need to deal with resonances), the C(V) is stable, and leakage is good. Supposedly, they may also exhibit self healing at high voltages (they don't reform like electrolytics), although I don't think that's intended, so if you try and end up with shorts, that's your problem..
I think the only vulnerability is they're sensitive to moisture (the opposite of drying out!) at high temperatures. So they end up with similar life*temp figures as electrolytics.
Tim
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It is clear now. Thank you all.
What is the general rule to connect de-coupling caps for IC, which has one VDD and a few GND pins that are far away from VDD pin, on a two-layer board ?
You cannot connect those pins as suggested here:
(http://i.stack.imgur.com/rRCDN.png)
Should I do it this way
(http://i.snag.gy/35cnc.jpg)
or this way (there are other GND pins on the opposite side and opposite corner of this IC)?
(http://i.snag.gy/Ce27d.jpg)
Or it does not matter in this case?
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Doesn't matter in your case. Just route it conviently
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It is clear now. Thank you all.
What is the general rule to connect de-coupling caps for IC, which has one VDD and a few GND pins that are far away from VDD pin, on a two-layer board ?
You cannot connect those pins as suggested here:
(http://i.stack.imgur.com/rRCDN.png)
a.-c. Doesn't matter. The cap is as near to the pins as possible (except in b., which requires a little clearance around the via). Routing the supply matters little, essentially not at all if using a 4 layer board.
d. Also acceptable on a 4 layer board. Not terrible on 2 layer either, and can help save some space (the cap can be pointed lengthwise with the pin, allowing nearby pins to route more easily around it)
e. Just dumb, obviously; but, any "sneak paths" you can get with nearby pours will only help. Stitch the pours to get the combined effects from d.-f.
f. Good, but not optimal: the supply does not see the lowest impedance. To achieve that, use several vias, as close alongside the capacitor as possible, flanking, so the distance between vias (and the loop from inner layer, up the vias, and across the capacitor) is as small and short as possible.
The reason stated on a. is dubious at best: to scale, there's maybe 5nH of inductance from cap to pin to supply plane -- in any of these examples except e. In no case is it avoided that "noise current flows into supply". In all of these examples, a sizable percentage of noise current will flow there, regardless, and that is as it should be: inner planes offer the lowest inductance and "highest speed" bypass available. In a 4 layer design, local bypass caps are almost entirely redundant! A few can be spread out along the plane, with some bulk caps to provide damping (not so much to provide bulk energy storage, despite what the name suggests).
If you require low noise techniques (isolating a noisy section from quiet surroundings, or vice versa), use filter chokes and a local, isolated supply plane section.
Tim