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Options for switching a 12V load with a 1.8V logic signal
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eddie1:
Thanks for such a long and detailed response!


--- Quote from: T3sl4co1l on January 20, 2020, 01:32:46 am ---Ah, okay.  You will be well served to understand SMPS in the first place (it's not clear what your knowledge level is here), and then to optimize them for efficiency.

--- End quote ---

I'd say just a very basic level of understanding so far. Enough to get a crude prototype working, but very, very, very far from what professionals like you or the engineers at TI, AD/LTC, etc. can do. My background is in software, only recently getting into hardware development. I happen to like optimization and working close to the metal, even in cases where it's not commercially viable, and abhor the "we've got 10 layers of virtualization + 100 more layers of abstraction but we'll just throw more hardware at it if it's too slow" mentality.


--- Quote from: T3sl4co1l on January 20, 2020, 01:32:46 am ---A good lesson might be more of the methodology to optimize things.  Measure subcircuits and see where the dominant losses are, and figure out ways to improve them locally.  Then take a step back and see if you can swap around the functionality of those circuits, replacing whole sets with lower consumption types.  Then repeat local optimization, etc.

--- End quote ---

Agreed. In a way that's what I've been doing here by focusing on the power stage, as I know that with the simplest pull-up approach it's going to be a sizable-enough source of loss.


--- Quote from: T3sl4co1l on January 20, 2020, 01:32:46 am ---A few years ago I did this exercise,

...

A purpose-made IC can absolutely beat the pants off this thing, easily 5x lower Iq I would expect.  But no one makes one for this exact function, nor enough building blocks (comparators, logic, etc.) with adequate speed-accuracy-Iq tradeoff.  So there's not much alternative.

--- End quote ---

That's a cool project! I eventually want to work on adding overcurrent protection to this as well (just as a safeguard to ensure an accidental short -- or hardware failure causing one -- doesn't result in smoke).


--- Quote from: T3sl4co1l on January 20, 2020, 01:32:46 am ---For example, make a high-side "bus hold" latch: two CMOS inverters in a loop, with a resistor in series with each output so one or the other can be overdriven by a stronger load.  Switch these with low side NMOS, driven from the MCU, complementary.  There's your level shift, and it doesn't consume any Iq.  Only 12V / R_series is drawn during switching, which can be say 100ns long.  (The limiting factor is actually not so much the resistance, but the total charge of the opposite side gate's input capacitance plus the drain capacitance of the other NMOS.  This can be some 10s of pF, which isn't terrible.)

--- End quote ---

Hmm, I don't completely understand. I get the concept of a bus-hold latch and get that CMOS inverters can be used to produce a 12V output from an MCU's logic low output, but how would the CMOS inverter ever be made to produce a logic low output without a 12V (or close to that -- whatever the logic high threshold is with a 12V Vcc) input?

I suppose a CMOS inverter could theoretically be used as a sort of level shifter by using the MCU pin (with NMOS in between) to low-side switch (i.e. ground or hi-Z) the inverter's ground and input pins, but I don't see how that's really any different from just driving a PMOS directly and floating the gate (which, as I understand, is not a robust solution).


--- Quote from: T3sl4co1l on January 20, 2020, 01:32:46 am ---BTW, PMOS performs about 2.5 times worse than NMOS, so there is a real advantage, saving on Qg * Fsw current draw.  Likewise, prefer a relatively small transistor (higher Rds(on), lower Qg(tot)), since conduction losses won't be your biggest problem here.

That's even an error that a lot of people make, even if they don't care about drive power: they see 4mΩ or whatever in the headline, and are sold on that.  What could be better, right?  Nevermind that the drain is 10nF at low bias, or the gate is 200nC.  And then they get socked with all these losses, and their interaction with stray inductances, and the whole thing keeps blowing up...

--- End quote ---

I'm glad to know I've been doing MOSFET shopping at least somewhat properly. :P Total gate charge is one of the metrics I sort by.


--- Quote from: T3sl4co1l on January 20, 2020, 01:32:46 am ---There are also worse ways, that can still be alright in special cases.  For example, a charge pump or DC restore circuit.  You have a 1.8V swing on an MCU pin; capacitor-couple that to the high side, with a resistor bleeding off charge so it idles at +12V.  Use something like RZM001P02, that only needs 1.8V drive.  The catch: the 12V supply must not vary more than a fraction of a volt, or the cap will dutifully turn on (or erroneously turn off) the transistor.  This makes startup and transient cases a bitch.

--- End quote ---

Speaking of that, one approach I considered was to use a voltage-doubling charge pump with multiple stages to increase the 1.8V supply to something over 12V to drive the MOSFET. That felt like a hack though -- boosting the 1.8V supply to 12V when there's already a 12V supply there, just because the boost can easily be switched from a 1.8V MCU pin. The upside is that it would allow me to get a voltage over 12V and use an NMOS. Maybe that kind of approach is still worth looking at further, even if it does feel like a hack?

The charge pump design I had in mind was (EEVblog #473). I was also able to quickly prototype that on a breadboard using my AD2 (which is really nice because it bundles a scope, DC power supply, pattern generator, logic analyzer, and some other tools).


--- Quote from: T3sl4co1l on January 20, 2020, 01:32:46 am ---
--- Quote ---Yes, but if I calculate (from data sheet specs) that a given BJT would need, say, 500 nA base current to switch this load, can I actually use a resistor that high (for that example, 24M at 12V) or is there some other consideration that will prevent it from working consistently? Sort of like how pull-up resistors on open drain signals theoretically could be 1M, but at the cost of robustness (picking up noise that switches the input erroneously).
--- End quote ---

Note that BJTs are just as voltage-controlled as MOSFETs, so you still need to charge and discharge that base voltage.  It's a lot less charge than a FET of the same dimensions, but you're at a disadvantage because you're doing it from 12V away.  In short, 24M gives a long time constant (10s µs, if that?).

Typical solution is a B-E resistor to aid turn-off.  (This also keeps collector leakage somewhat lower.  Roughly speaking, C-B leakage flows into the base and gets multiplied by hFE.  This is also roughly why Vcbo > Vceo: the leakage current contributes to a lower breakdown voltage.)

--- End quote ---

I had a feeling there was some practical reason such a high base resistor wouldn't work on its own. Thanks for confirming!


--- Quote from: T3sl4co1l on January 20, 2020, 01:32:46 am ---
--- Quote ---Is this one such part you're referring to? Just want to check because Linear tends to have good technical descriptions in their data sheets so I can research this further.

--- End quote ---

Like this, used one a bunch of years ago, still have the number handy:
https://www.analog.com/media/en/technical-documentation/data-sheets/3481fc.pdf
Note the switch voltage drop is a fraction of what LT1074/6 does, because of the bootstrap.  All the '74/6 can do is pull the base up to VCC, and the emitter hangs down by 0.7V or so per transistor.  Supply goes down to 3.something V, whereas discrete MOSFETs aren't much use below 5-8V.

There are some old chips working in such a domain, https://datasheets.maximintegrated.com/en/ds/MAX631-MAX633.pdf for example.  (They're still available, amazingly enough, but are priced like an old boutique part.  Not that they're exactly relevant, being boost type.)  Voltage rating suggests metal-gate CMOS (ala CD4000, 74C00 family).

Note that the block diagram is much more than a comparator and driver, and these are still pretty basic devices.

--- End quote ---

Thanks! I'll read through the data sheets and also look for other documents (app notes, etc.) that might be useful.


--- Quote from: T3sl4co1l on January 20, 2020, 01:32:46 am ---At low currents, you'll probably be fine with hysteretic or PFM (or "pulse skipping") operation, but the peak current (and preferably the average as well) needs to be monitored to ensure safe operation.

--- End quote ---

Is the current monitoring just for short circuit protection?


--- Quote from: T3sl4co1l on January 20, 2020, 01:32:46 am ---You can use a few-us comparator, but that delay needs to be a small fraction of the total cycle, so you'll be in the low 10s kHz doing it that way, and you need big inductors.  This isn't a very cost-effective approach.  But yeah, you can certainly develop an understanding this way.

--- End quote ---

Hmm. The Atmel SAM L10 and L21 chips seem to have incredibly good comparator specs, far better than any comparator IC or other MCU comparator I can find (including EFM32). Take a look at page 1029 (using the page numbers in the footer) of the L21 data sheet.

They're claiming 560 ns typical, 1.41 us max at 289 nA typical, 2.2 uA max; or 330 ns typical, 2.7 us max at 549 nA typical, 2.495 uA max. Those are all +/- 100 mV overdrive.

The L10 claims similarly impressive specs.

Are these realistic or too good to be true? Heck, I'm pretty sure I've read a comment from you in some other thread saying Atmel's analog design process is poor, which just further makes me question how realistic their best-in-class numbers are.

How big of an inductor are you talking? I noticed the LTC3388 requires 22 uH minimum and has recommendations up to 100 uH, which is on the bigger side of any regulator ICs I've looked at.


--- Quote from: T3sl4co1l on January 20, 2020, 01:32:46 am ---A lot of regulators (of ordinary ratings, e.g. 30V input) boast low Iq, though it varies whether it's in shutdown or idle conditions.  Can always wrap a hysteresis comparator around one, forcing burst-mode output while maintaining reasonable efficiency.  Note that the comparator only needs to respond to voltage changes, i.e., 10s or even 100s of µs.  The downside is a lot of output voltage ripple, but that's just going to happen in this domain, and again, you can LDO it, taking off only a fraction of a volt this time, to clean it up.

--- End quote ---

They do, but there are a lot of varying definitions of "low IQ" seemingly based on the product they're trying to sell. I've not seen any (other than LTC3388) where the IQ would not be a significant efficiency hit at, say, 100 uA load current.
T3sl4co1l:

--- Quote from: eddie1 on January 20, 2020, 11:36:31 pm ---Hmm, I don't completely understand. I get the concept of a bus-hold latch and get that CMOS inverters can be used to produce a 12V output from an MCU's logic low output, but how would the CMOS inverter ever be made to produce a logic low output without a 12V (or close to that -- whatever the logic high threshold is with a 12V Vcc) input?
--- End quote ---

Use an NMOS (driven by MCU pin) to tug one or the other input low. :)

So one inverter output connects to a resistor, which connects to the other inverter input.  NMOS drain to input, source to GND, gate to MCU.  Double it, with the inverters in a ring.  MCU outputs alternately pulse high to change state.  It's a somewhat crude implementation of an RS flip-flop.



--- Quote ---Is the current monitoring just for short circuit protection?

--- End quote ---

It can be used for dynamics as well.  The key fact is this: a switched-inductor, voltage source converter, acts as an integrator.

In the same way that you don't know the instantaneous value of an accumulator (i.e., a = a + x) until you read it, you don't know what current is in the inductor until you measure it.  In software, the hazard might be overflow (a pretty bad defect in a DSP path), but IRL, the hazard is releasing magic smoke.

At low power, you're very likely going to be in DCM, where you can make some assumptions.  If the inductor current is definitely going to zero every cycle, well, the accumulator resets, so you don't have to worry about that.

But therein lies the problem: if your assumption ever gets broken, so does your circuit.  Short circuit is a typical case, yes, but you don't want to neglect startup or load transients, either!

It's easy to get the mean case right; it's all about the edge cases.  You can program almost entirely by feeling out the edges of a problem, or an algorithm, with little or no need to worry about the average case.  Same here. :)

Not that it's a huge problem even then, since you could just use oversized (or undersized, for that matter) transistors, or an inductor with relatively high resistance, etc.  These all have impacts on cost, size* or efficiency, of course.

*Not that you can actually get a minimal sized transistor: RF MOSFETs are pretty much gone nowadays, so there's not much chance of using a 10mA 20V part unless you want to go digging through old stock.  And RF types have never been the cheapest, even though they have the smallest active area.  So, this particular economy only applies to monolithic design, if at all; go figure!



--- Quote ---Hmm. The Atmel SAM L10 and L21 chips seem to have incredibly good comparator specs, far better than any comparator IC or other MCU comparator I can find (including EFM32). Take a look at page 1029 (using the page numbers in the footer) of the L21 data sheet.

They're claiming 560 ns typical, 1.41 us max at 289 nA typical, 2.2 uA max; or 330 ns typical, 2.7 us max at 549 nA typical, 2.495 uA max. Those are all +/- 100 mV overdrive.
--- End quote ---

Dunno.  100mV is a lot of overdrive (you might use up all of that in a shunt resistor just on base level alone -- there are a lot of switching controllers out there that use a 50-200mV range current sense signal), but sub-1uA is awfully optimistic, even so.

I wonder if it's possible by implementing the function in fine pitch circuitry (<= 100nm scale?).  My understanding is analog performance drops off below 250nm or so, which should be performance in terms of bandwidth at power and efficiency, which will be relevant to the performance of something like a comparator.  And that's around the scale of most CMOS, so no one should be doing anything terribly remarkable.

Could also be that they're always very hesitant to give any kind of confidence behind power consumption numbers.  Rightfully so, as it depends completely on code.  But this should be simple enough not to make an orders-of-magnitude underestimate.



--- Quote ---Are these realistic or too good to be true? Heck, I'm pretty sure I've read a comment from you in some other thread saying Atmel's analog design process is poor, which just further makes me question how realistic their best-in-class numbers are.
--- End quote ---

Atmel is a big company, with a lot of products, designed by a lot of people, over a long time.  That comment was about classic ATMEGA parts, which I heard from someone else (I haven't tested it myself, mind; other than the ADC and REF specs, which are right there in the datasheet).  I haven't heard anything about the other families (XMEGAs, newer MEGAs, SAMs, etc.). 

TI for example has their share of lemons, both in parts and documentation.  Even ADI has made a few boners (most notably: a 24-bit ADC with "SPI" interface, that doesn't reset clock state when CS is deasserted; if it ever misses a SCK edge, or receives an extra glitch, all data until the end of time will be gibberish; the only cure is a power cycle!).  It would be unfair to judge a large, heterogeneous organization by just one of its parts, so there's not much you can generalize from these, just gotta keep testing parts and getting familiar with them.



--- Quote ---How big of an inductor are you talking? I noticed the LTC3388 requires 22 uH minimum and has recommendations up to 100 uH, which is on the bigger side of any regulator ICs I've looked at.
--- End quote ---

If you plugged in numbers like: 12V in, 5V 10mA out, 20kHz, into a calculator, you'd get something like 8mH for BCM.  And proportionally more for proportionally lower currents, of course.

That's not so terrible (small, 10s mH inductors are certainly available), but inductances that large are I think hard to find with low losses and small sizes.  Q is roughly proportional to sqrt(F), so the low frequency just keeps killing Q (and thus efficiency), and the small size doesn't help.  The frequency of peak Q tracks with the linear size of the part, more or less, so a small part is extra disadvantaged at low frequencies.

Smaller inductances imply higher dI/dt, implying faster comparators to avoid fault conditions.

Tim
Zero999:
Can't you just use a standard CMOS logic level shifter circuit to drive the P-MOSFET?

MP1, MN2, MP2 and MN3 can be replaced with low voltage CMOS inverter gates, such as the 74LVC2G04. MN1 & MN4 can be the BS138 and MP3 & MP4, the BSS84.

https://wiki.analog.com/university/courses/electronics/electronics-lab-voltage-level-shifter

http://www.ti.com/lit/ds/symlink/sn74lvc2g04.pdf
http://www.farnell.com/datasheets/2298371.pdf
https://www.onsemi.com/pub/Collateral/BSS138-D.PDF
magic:
I wonder if flyback would be feasible (not sure how bad transformer losses are compare to a single inductor). This can be made with low side switching and everyone is happy.

As for small general purpose MOSFETs, anything with AK suffix from NXP (NX3020AK, NX7002AK, BSS138/84AK), CSD15380F3 (:scared:), FDV301N, some SSM3xxxx from Toshiba...
eddie1:

--- Quote from: T3sl4co1l on January 21, 2020, 02:13:07 am ---Use an NMOS (driven by MCU pin) to tug one or the other input low. :)

So one inverter output connects to a resistor, which connects to the other inverter input.  NMOS drain to input, source to GND, gate to MCU.  Double it, with the inverters in a ring.  MCU outputs alternately pulse high to change state.  It's a somewhat crude implementation of an RS flip-flop.

--- End quote ---

Ah, I think I have an idea now of how this is supposed to work. I'll simulate it.


--- Quote from: T3sl4co1l on January 21, 2020, 02:13:07 am ---
--- Quote ---Is the current monitoring just for short circuit protection?

--- End quote ---

It can be used for dynamics as well.  The key fact is this: a switched-inductor, voltage source converter, acts as an integrator.

In the same way that you don't know the instantaneous value of an accumulator (i.e., a = a + x) until you read it, you don't know what current is in the inductor until you measure it.  In software, the hazard might be overflow (a pretty bad defect in a DSP path), but IRL, the hazard is releasing magic smoke.

At low power, you're very likely going to be in DCM, where you can make some assumptions.  If the inductor current is definitely going to zero every cycle, well, the accumulator resets, so you don't have to worry about that.

But therein lies the problem: if your assumption ever gets broken, so does your circuit.  Short circuit is a typical case, yes, but you don't want to neglect startup or load transients, either!

--- End quote ---

So this, if I understand correctly, is about making sure the inductor isn't overcharged beyond its rated current limit (or it becomes a fire hazard).

Even if the load current and inductor size were such that it was not operating in DCM, does hysteretic control not effectively take care of this? The comparator isn't going to trip until the output voltage drops below a certain point, which presumably means there's not some abundance of current stored in the inductor.

There's a need to make sure the peak load current isn't higher than what the circuit can support, of course (whether that's a short or someone trying to power a high-end Nvidia card off a micropower supply :P).

This does make me question whether there's something basic in "buck converters 101" that I'm missing. The LTC3388 data sheet mentions ramping up the inductor current to 150 mA and then down to 0 mA, as if they're doing some kind of current monitoring similar to what you mention. (The LTC3388 uses hysteretic control.) The part I don't get is how they can do some kind of current control like this without affecting output voltage regulation. Surely if they keep the PMOS on until the inductor current reaches 150 mA even if the comparator is outputting 0 (voltage now in regulation), that's going to result in the output voltage overshooting the intended target?


--- Quote from: T3sl4co1l on January 21, 2020, 02:13:07 am ---
--- Quote ---Hmm. The Atmel SAM L10 and L21 chips seem to have incredibly good comparator specs, far better than any comparator IC or other MCU comparator I can find (including EFM32). Take a look at page 1029 (using the page numbers in the footer) of the L21 data sheet.

They're claiming 560 ns typical, 1.41 us max at 289 nA typical, 2.2 uA max; or 330 ns typical, 2.7 us max at 549 nA typical, 2.495 uA max. Those are all +/- 100 mV overdrive.
--- End quote ---

Dunno.  100mV is a lot of overdrive (you might use up all of that in a shunt resistor just on base level alone -- there are a lot of switching controllers out there that use a 50-200mV range current sense signal), but sub-1uA is awfully optimistic, even so.
--- End quote ---

100 mV is definitely a lot; I wish they provided numbers for 10 mV since that (I think) is more in line with the real use case here. Most MCU vendors don't seem to provide specs lower than 100 mV.


--- Quote from: T3sl4co1l on January 21, 2020, 02:13:07 am ---
--- Quote ---Are these realistic or too good to be true? Heck, I'm pretty sure I've read a comment from you in some other thread saying Atmel's analog design process is poor, which just further makes me question how realistic their best-in-class numbers are.
--- End quote ---

Atmel is a big company, with a lot of products, designed by a lot of people, over a long time.  That comment was about classic ATMEGA parts, which I heard from someone else (I haven't tested it myself, mind; other than the ADC and REF specs, which are right there in the datasheet).  I haven't heard anything about the other families (XMEGAs, newer MEGAs, SAMs, etc.).

--- End quote ---

Fair enough!

I'm semi-curious about the SAM parts, but I'm not sure if my AD2 scope (which is pretty low-end; the AD2's value is in its portability, ease of use, and integration, not in raw specs of each feature) is enough to accurately measure that. Might be an excuse to get a proper scope though. :P


--- Quote from: T3sl4co1l on January 21, 2020, 02:13:07 am ---
--- Quote ---How big of an inductor are you talking? I noticed the LTC3388 requires 22 uH minimum and has recommendations up to 100 uH, which is on the bigger side of any regulator ICs I've looked at.
--- End quote ---

If you plugged in numbers like: 12V in, 5V 10mA out, 20kHz, into a calculator, you'd get something like 8mH for BCM.  And proportionally more for proportionally lower currents, of course.

That's not so terrible (small, 10s mH inductors are certainly available), but inductances that large are I think hard to find with low losses and small sizes.  Q is roughly proportional to sqrt(F), so the low frequency just keeps killing Q (and thus efficiency), and the small size doesn't help.  The frequency of peak Q tracks with the linear size of the part, more or less, so a small part is extra disadvantaged at low frequencies.

Smaller inductances imply higher dI/dt, implying faster comparators to avoid fault conditions.

--- End quote ---

Classic engineering tradeoff, I guess -- higher inductance and lower switching speed/losses but increased inductor losses for the same physical size.

For now, I'm thinking the best thing to do is use a higher-power, faster comparator with a hysteretic control algorithm (which means the switching speed won't be limited to the available clock). I can probe it and optimize it later, testing changes like dropping the comparator speed (and power). Since standalone comparator ICs are specced for lower overdrives, I ordered an ST TS3021 which gets to about 50 ns typical at 20 mV. (TI has a similar part with similar specs, but it requires a higher input voltage. I could use it via the charge pump doubler, but why bother when the ST part is similar and supports 1.8V directly.)

note: The EFM32TG11 (and probably all the other EFM32s; I didn't look) require a higher (2.1V+) analog supply voltage for comparator settings faster than 3.7 us. It's doable, but for prototyping easier to just get another chip (plus it's specced for smaller overdrive).


--- Quote from: Zero999 on January 21, 2020, 09:49:42 am ---Can't you just use a standard CMOS logic level shifter circuit to drive the P-MOSFET?

MP1, MN2, MP2 and MN3 can be replaced with low voltage CMOS inverter gates, such as the 74LVC2G04. MN1 & MN4 can be the BS138 and MP3 & MP4, the BSS84.

--- End quote ---

Thanks! I'll simulate and probe that one to try to better understand it.
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